Synopsys 公司 2008 年春季研讨会
February 29, 2008
研讨会简介
无论在无线、移动与家用电器等传统的功耗敏感性应用中，还是在现今的既需要满足节能要求又要达到高性能目标的应用中，功耗在半导体领域逐渐成为一个 关键性问题。在设计中缩小工艺尺寸使得功耗问题更加突出，泄露功耗渐成为占总功耗一半的来源。而且，功耗密度集中在这些较小尺寸上，以至于不能正确提供能 量或者完成能量消散。
参加Synopsys 低功耗研讨会，了解 Synopsys 的端到端、硅验证高级低功耗解决方案。研讨会期间，Synopsys 与将与其他在低功耗领域处于前沿的公司探讨有关低功耗挑战及其解决方法的前瞻性看法。本研讨会还将就 Synopsys 降低功耗的全面实现和验证的方法进行指导。
参加研讨会人员：
项目经理、设计工程师、CAD 经理、验证工程师与经理
研讨会内容：
UPF: Accellera’s Unified Power Format (UPF 1.0) has become the industry standard for defining low power intent. This seminar will include an introduction to UPF, and will focus on the core set of constructs that are essential for the development of today’s low power designs. Syntax for applying advanced low power techniques such as power gating, multi-voltage, and state retention will be covered.
Low Power Design Techniques: Specific techniques that will be discussed are: voltage aware simulation and power state analysis, including Synopsys’ unique power state transition validation; power state table (PST) implementation; power switch cell (MTCMOS) layout, analysis, and optimization; and power-optimized automatic test pattern generation (ATPG). The final steps will highlight equivalence checking of the final netlist to the golden RTL and UPF specification files, along with voltage-aware sign-off, with concurrent timing, signal integrity (SI), and power analysis.
Low Power Methodology Manual: The flow and demos will follow the recommended methodologies outlined in the Low Power Methodology Manual (LPMM), co-authored by ARM and Synopsys.
Insight China
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SNUG
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White Pager
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Good Chip Series
