Synopsys 2010 用户大会暨技术研讨会
July 5, 2010
北京
日期：2010年8月9日（星期一）
地点：北京香格里拉饭店 一层大宴会厅
地址：北京市紫竹院路29号
日程安排:
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8:30-9:00
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Registration
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9:00-9:15
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Opening by Robert Li —– Synopsys China Country Manager
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9:15-9:45
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Keynote Speech by Frank Lee —– Synopsys Vice President
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9:45-10:15
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Guest Speech by Roger Luo —–TSMC China Country Manager
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10:15-10:30
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SNUG Award Ceremony
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10:30-10:45
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Break
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Galaxy
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Low Power
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SNUG Award Paper
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IP and Prototyping
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Verification
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10:45-11:45
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IC Design Challenges & Galaxy Overview (Eddie Hsu) |
10:45-11:15
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Overview (Larry Vivolo) |
10:45-11:30 |
基于Magellan的eDram控制器验证 |
10:45-11:30 | Implementing USB 3.0 on Your SoC: IP Instantiation to Compliance Testing (Haoping Liu) |
10:45-11:45 | Discovery Verification Platform Overview (Albert Chiang) |
| 11:15-12:00 | Low Power Verification Update (Krishna Balachandran) |
11:30-12:15 | Physical Verification in 65nm Design (Leadcore) |
11:30-12:15 | Definition Multimedia Interface – Understanding HDMI 1.4
(Tom Liu) |
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11:45-13:00
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Lunch | 12:00-13:00 | Lunch | 12:15-13:15 | Lunch | 12:15-13:15 | Lunch | 11:45-13:00 | Lunch |
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12:30
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LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo |
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13:00-14:00
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RTL Synthesis & TEST (Alvin Hsu) |
13:00-14:30 | Low Power Implementation Update (BJ: Li Ang/Zhizhong) (SH: Qiuer/David) (SZ: Kenny) |
13:15-14:00 | 低功耗验证解决方案 (Vimicro Corporation) |
13:15-14:00 | In-system Calibration for High-Speed DDR Interface IP (Fong Li) |
13:00-15:00 | VCS Product Update (Albert Chiang) |
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14:00-14.:45
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Signoff (STA, SI, Extraction) (Jack Ting) |
14:30-15:00 | Visual UPF GUI (Larry Vivolo) |
14:00-14:45 | Using Multi-Bit Flip-Flop for Clock Power Saving by DesignCompiler (Faraday Technology Corporation) |
14:00-15:00 | System Design Overview: from Concept to Implementation (BJ/SH:William Lock) (SZ: Zhizhi/Xiaowei) |
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14:45-15:00
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Break | 15:00-15:15 | Break | 14:45-15:00 | Break | 15:00-15:15 | Break | 15:00-15:15 | Break |
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15:00-17:00
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Physical Design & Verification (Dan Huang/Siao Lung Hwang) |
15:15-16:15 | Extreme Low-Power Datapath Design with DesignWare minPower Components (Jay Chiang) |
15:15-16:30 | Analog & Mixed-Signal Circuit Simulation Update (Peter Wang) |
15:15-15:45 | Bigger, Faster, Better – An Introduction to HAPS 60 (Neil Songcuan) |
15:15-16:00 | Verification Methodology Update (Albert Chiang) |
| 16:15-17:00 | In-Design Rail Analysis for Faster Power Network Design Closure (Jack Ting) |
15:45-17:00 | From SoC to FPGA-based Prototyping: Designware IP in Two Worlds (Neil Songcuan) |
16:15-17:00 | Magellan Product Update (Krishna Balachandran) |
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17:00-17:15
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Lucky draw
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联系人：戴景雯
邮件：jwdai@synopsys.com
电话：010-5986 0651
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上海
时间：2010年8月11日（星期三）
地点：上海龙之梦丽晶大酒店 四层大宴会厅
地址：上海市长宁区延安西路1116号
日程安排:
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8:30-9:00
|
Registration
|
||||||||
|
9:00-9:15
|
Opening by Robert Li —– Synopsys China Country Manager
|
||||||||
|
9:15-9:45
|
Keynote Speech by Frank Lee —– Synopsys Vice President
|
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9:45-10:15
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Guest Speech by Fu Hui —– Managing director of Infineon Technologies Xi’an Co., Ltd
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10:15-10:30
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SNUG Award Ceremony
|
||||||||
|
10:30-10:45
|
Break
|
||||||||
|
Galaxy
|
Low Power
|
SNUG Award Paper
|
IP and Prototyping
|
Verification
|
|||||
|
10:45-11:45
|
IC Design Challenges & Galaxy Overview (Eddie Hsu) |
10:45-11:15
|
Overview
(Larry Vivolo) |
10:45-11:30 |
深亚微米SoC晶体管级静态时序分析与建模 (National High Performance IC (Shanghai) Design Center) |
10:45-11:30 | Implementing USB 3.0 on Your SoC: IP Instantiation to Compliance Testing
(Haoping Liu) |
10:45-11:45 | Discovery Verification Platform Overview
(Albert Chiang) |
| 11:15-12:00 | Low Power Verification Update
(Krishna Balachandran) |
11:30-12:15 | 基于Synopsys CHIPit平台的数字全高清视频N2M芯片事务级验证
(Pixelworks) |
11:30-12:15 | Definition Multimedia Interface – Understanding HDMI 1.4
(Tom Liu) |
||||
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11:45-13:00
|
Lunch | 12:00-13:00 | Lunch | 12:15-13:15 | Lunch | 12:15-13:15 | Lunch | 11:45-13:00 | Lunch |
|
12:30
|
LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo |
|
13:00-14:00
|
RTL Synthesis & TEST
(Alvin Hsu) |
13:00-14:30 | Low Power Implementation Update
(BJ: Li Ang/Zhizhong) (SH: Qiuer/David) (SZ: Kenny) |
13:15-14:00 | Minimizing Clock Latency with IC Compiler
(Brite Semiconductor) |
13:15-14:00 | In-system Calibration for High-Speed DDR Interface IP
(Fong Li) |
13:00-15:00 | VCS Product Update
(Albert Chiang) |
|
14:00-14.:45
|
Signoff (STA, SI, Extraction)
(Jack Ting) |
14:30-15:00 | Visual UPF GUI
(Larry Vivolo) |
14:00-14:45 | PVE验证解决方案
(Vimicro Corporation) |
14:00-15:00 | System Design Overview: from Concept to Implementation
(BJ/SH:William Lock) (SZ: Zhizhi/Xiaowei) |
||
|
14:45-15:00
|
Break | 15:00-15:15 | Break | 14:45-15:00 | Break | 15:00-15:15 | Break | 15:00-15:15 | Break |
|
15:00-17:00
|
Physical Design & Verification
(Dan Huang/Siao Lung Hwang) |
15:15-16:15 | Extreme Low-Power Datapath Design with DesignWare minPower Components
(Jay Chiang) |
15:15-16:30 | Analog & Mixed-Signal Circuit Simulation Update
(Peter Wang) |
15:15-15:45 | Bigger, Faster, Better – An Introduction to HAPS 60
(Neil Songcuan) |
15:15-16:00 | Verification Methodology Update
(Albert Chiang) |
| 16:15-17:00 | In-Design Rail Analysis for Faster Power Network Design Closure
(Jack Ting) |
15:45-17:00 | From SoC to FPGA-based Prototyping: Designware IP in Two Worlds
(Neil Songcuan) |
16:15-17:00 | Magellan Product Update
(Krishna Balachandran) |
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17:00-17:15
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Lucky draw
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18:00-20:00
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R&D night
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联系人：刘佳
邮件：jialiu@synopsys.com
电话：021-2307 2082
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深圳
日期：2010年8月13日（星期五）
地点：深圳威尼斯皇冠假日酒店 一层大宴会厅
地址：深圳市华侨城深南大道9026号
|
8:30-9:00
|
Registration
|
||||||
|
9:00-9:15
|
Opening by Robert Li —– Synopsys China Country Manager
|
||||||
|
9:15-10:15
|
Keynote Speech by Frank Lee —– Synopsys Vice President
|
||||||
|
10:15-10:30
|
SNUG Award Ceremony
|
||||||
|
10:30-10:45
|
Break
|
||||||
|
Galaxy
|
Low Power
|
IP and Prototyping
|
Verification
|
||||
|
10:45-11:45
|
IC Design Challenges & Galaxy Overview (Eddie Hsu) |
10:45-11:15
|
Overview
(Larry Vivolo) |
10:45-11:30 | Implementing USB 3.0 on Your SoC: IP Instantiation to Compliance Testing
(Haoping Liu) |
10:45-11:45 | Discovery Verification Platform Overview
(Albert Chiang) |
| 11:15-12:00 | Low Power Verification Update
(Krishna Balachandran) |
11:30-12:15 | Definition Multimedia Interface – Understanding HDMI 1.4
(Tom Liu) |
||||
|
11:45-13:00
|
Lunch | 12:00-13:00 | Lunch | 12:15-13:15 | Lunch | 11:45-13:00 | Lunch |
|
12:30
|
LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo | 12:30 | LYNX Demo |
|
13:00-14:00
|
RTL Synthesis & TEST
(Alvin Hsu) |
13:00-14:30 | Low Power Implementation Update
(BJ: Li Ang/Zhizhong) |
13:15-14:00 | In-system Calibration for High-Speed DDR Interface IP
(Fong Li) |
13:00-15:00 | VCS Product Update
(Albert Chiang) |
|
14:00-14.:45
|
Signoff (STA, SI, Extraction)
(Jack Ting) |
14:30-15:00 | Visual UPF GUI
(Larry Vivolo) |
14:00-15:00 | System Design Overview: from Concept to Implementation
(BJ/SH:William Lock) |
||
|
14:45-15:00
|
Break | 15:00-15:15 | Break | 15:00-15:15 | Break | 15:00-15:15 | Break |
|
15:00-17:00
|
Physical Design & Verification
(Dan Huang/Siao Lung Hwang) |
15:15-16:15 | Extreme Low-Power Datapath Design with DesignWare minPower Components
(Jay Chiang) |
15:15-15:45 | Bigger, Faster, Better – An Introduction to HAPS 60
(Neil Songcuan) |
15:15-16:00 | Verification Methodology Update
(Albert Chiang) |
| 16:15-17:00 | In-Design Rail Analysis for Faster Power Network Design Closure
(Jack Ting) |
15:45-17:00 | From SoC to FPGA-based Prototyping: Designware IP in Two Worlds
(Neil Songcuan) |
16:15-17:00 | Magellan Product Update
(Krishna Balachandran) |
||
|
17:00-17:15
|
Lucky draw
|
||||||
联系人：王懿
邮件：jojowang@synopsys.com
电话：0755-82519830
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