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Limiting the number of Eigenvectors for a 90nm Contact AEI OPC Model


Chi-Yuan Hung, Bin Zhang, ZeXi Deng, Jian Zhang and GuoQiang Xing
Logic Technology Development and Manufacturing Center
Semiconductor Manufacturing International Corporation
Phone: +86-21-50802000 x 19556, E-mail:Odd_Hung@smics.com

1) ABSTRACT

As wavelength reduction in exposure systems does not keep up with rate of IC design rule shrink, Litho RET, Etch trimming and OPC techniques are now used extensively as part of the integrated patterning flow. Here, we collected a large number of 90nm contact CD datasets, from mask, ADI to AEI. Based on those datasets, we developed a variable etch bias AEI model for 90nm contact layer. In this paper, we investigated various modeling strategies to streamline this OPC modeling approach. Multiple regression method is used to fit CTR and CTE models.

We will show that an extra long range Loading Kernel (additional to a well-fitted ADI model ) may not meet the fitting criteria mainly due to the fact that models with too many eigenvectors would have a tendency to over-fit-and-correct CD curves. By limiting the number of parameters in our model OPC algorithm, we achieved a 90nm Contact Model with OPC empirical data fitting error within +(-)2nm in Synopsys ProGen platform. On wafer verification data confirmed this result with excellent through-pitch OPC residual error.

KEYWORD: Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), After Development Inspection (ADI), After Etch Inspection (AEI), Constant Threshold Resist model (CTR model), Constant Threshold Etch model (CTE model),

2) INTRODUCTION

OPC is the centerpiece of Patterning technology. It directly impacts chip performance; and it accounts for a large portion of the total cost of chip fabrication. Therefore, the accuracy, fidelity and flexibility of OPC performance become more and more important.

Normally speaking, a complete process from design to etched layouts may interpreted as:

Here in this paper, I dropped the Tresist part ( in Synopsys ProGen Modeling algorithm ) due to this part can almost NOT “seen” after out etch process. So, I reduced our model correction into:

Besides, we also demonstrate and compare other Modeling approaches, and finally, the results of real wafer verification data will be shown down to the AEI.

3) Modeling Experiment

Traditionally, Model-Based OPC only use ADI Model and treat Design Database as Model-Based OPC’s simulation & correction target, which can NOT handles some non-constant Etch Bias processes.

And current practice most likely use:

1) Run Rule-Based OPC to re-target some non-constant Etch bias patterns before Model-Based OPC, which losses Database hierarchy and takes tremendous OPC processing time. Besides, 2D structures may cause some strange jogs.

2) Used ADI Model rigidly fits the AEI data (High failure rate):

Traditionally, ADI Model use : Optical Kernel + Resist Kernel + one Loading Kernel: Optical Kernel : Present optical behavior for Scanner, mask….etc.

Resist Kernel : Bring Resist behavior into model, for example diffusion length.

Loading Kernel: Introduce short range loading effect, for example local pattern density.

See Fig.3. This kind of model can NOT cover non-constant Etch bias process due to Etch process has Long range loading effect.

3) Add a new Etch Kernel additional to current ADI Model to modulate the Etch-Photo proximity difference ( Complicated, performances not so good ):

Conventionally, AEI Model use : Optical Kernel + Resist Kernel + two Loading Kernel: Optical Kernel, Resist Kernel and one Loading Kernel are just as ADI model

The second Loading Kernel: Introduce long range loading effect.

See Fig.4. This kind of model can cover non-constant Etch bias process, but still introduced some disturbance of photoresist which may not present in AEI wafer data.

Here, we take 90nm Contact AEI data for example:

Fig1. 90nm Contact layer ADI & AEI wafer data. Design rule is 120nm.

Fig 2. : AEI-ADI Etch of Fig.1. (Non-Constant Etch Bias )

Fig3. Use traditionally ADI Model (Optical Kernel + Resist Kernel + one Loading Kernel) to rigidly fit AEI data. On rule proximity can be fit well, but other proximity can NOT be fit well due to there is Long range Loading effect.
Fig 4.Introduce a new long range Loading Kernel to ADI Model, which can cover non-constant Etch bias process, but still some resist kernel caused disturbance may not be eliminated.

Our invention is to set up Etch model by introducing a new algorithm to reduce the ADI wafer data proximity disturbance. By using Optical Kernel + Loading Kernel only, we successfully setup a 90nm Contact Etch Model which performs OPC fitting error within +-2nm. (See Fig 5.)

Fig 5. : By using Optical Kernel + Loading Kernel only, we successfully setup a 90nm Contact Etch Model (Not including Resist Kernel is to avoid ADI proximity disturbance, which may not be seen in pure AEI wafer data.)

4) Test Pattern

This CTE Model is built by fitting CD measurements data, which is collected from the test patterns. There are two types of test patterns: (1) Modeling test patters, and (2) verification test pattern. The Modeling test pattern is mainly designed to use a limited number of test structures for which people can measure CD values to generate models resulting in OPC precision within sub-90nm Contact layer design rules. The basic structure for the modeling test pattern including 1-D, 2-D proximity and linearity structures (Fig.6.):

Fig.6. Sub-90nm Contact layer Modeling test pattern

The modeling test pattern is deigned to contain sampling ability of different points in the parameter space, which includes entire frequency response of the patterning process transfer function.

About the verification test pattern we put some experimental sets and a control set ( the structure is very similar to Fig.6. but exclusive of Modeling patterns ). Simulation will be applied on this test pattern and compared to experimental measurements. The verification test pattern also contains more complicated and specialized structures such as SRAM cells and some 2-D feature combinations.

All our CD measurements are collected ( both ADI & AEI ) on HITACHI S-9260 CD-SEM. Besides, both modeling and verification data presented through this paper, we used at least three times’ wafer data for average.

5) Results

This from OPC modeling algorithm to wafer verification flow makes extensive use of the Synopsys family of products. Hercules was used to check 1-D, 2-D and some more complicated chip layouts’ DRC results. Two DRC violations were found in our specialized cell structure (see Fig.8.). The modeling algorithms, including this CTE and other experimental “limped” models, were fitted and built-up on Synopsys ProGen platform. Proteus took part in OPC implementation and correction for mask layouts. And, the following verification results were simulated by Prospector and ICworkbench.

With this alternative CTE approach. We achieved a 90nm Contact Model with OPC empirical data fitting error within +-2nm on Synopsys ProGen platform. And, the wafer verification datasets showed only 3 = 7.82 nm of through-pitch OPC residual error, compared to Prospector simulation residue error 3 of 8 nm, Fig.7. :

Fig.7 Wafer verification datasets showed only 3 = 7.82 nm of through-pitch OPC residual AEI CD error (Prospector simulation residue error 3 of 8 nm )

Fig.8. 2-D simulation (SRAM cell) v.s. wafer experiment images.

In Fig.8. we can see that even two design geometries violate the Design Rule (, potentially to become process weak points), our approach of Litho RET plus Etch trimming and CTE OPC combined tech flow is able to aid in the image transfer of design onto silicon wafer

6)Conclusion:

Extensive usage of Litho RET, Etch trimming and OPC techniques has become common practice in the integrated patterning flow for 90nm and beyond. In this paper, we discussed our approach to use OPC for both etch and litho through-pitch bias correction for a 90nm contact layer. It was revealed that an extra long range Loading Kernel, additional to a well-fitted ADI model, may not successfully meet the fitting criteria we want. And with the high level of programmability of the Synopsys OPC engine that was used to generate the modeling algorithms to enable the flexibility required. Therefore, in stead of using conventional lumped model, here we introduced an alternative modeling approach to reduce our model correction into:

to limit the number of parameters in our model OPC algorithm. We achieved a 90nm Contact Model with OPC empirical data fitting error within +-2nm, and the wafer verification datasets showed only 3 = 7.82 nm of through-pitch OPC residual error by using our Constant Threshold Etch Model, compared to Prospector simulation residue error 3 of 8 nm.

7) Acknowledgments:

The authors would like to acknowledge Jason Huang and Jiang Yan from Synopsys for assisting in modeling characterization and evaluation.

8) Reference:

[1] J.P. Stirniman, M.L. Rieger, SPIE Proc. Optical/Laser Microlithography X, Vol. 3051, p294, 1997.

[2] Daniel F. Beale, James P. Shiely, Lawrence L. Melvin III, Michael L, Rieger, “Advanced Model Formulation for Optical and Proximity Correction”, SPIE 2004.

[3] Daniel F. Beale, James P. Shiely, Michael L, Rieger, “Multiple Stage Optical Proximity Correction”, SPIE 2004.