2005论文集
Mixed-signal verification of pipeline Analog-to-digital converter (ADC) prototype
Improve Synthesis Results with Useful Clock Skew
Integrated Co-Simulation and Verification for Microprocessor on VCSTM Platform
Writing a RVM-Compliant AHB Master Transactor
A VIP based SoC architecture evaluation methodology
Random Verification Using VCS Native Testbench
Using VERA to test Enhanced Secure Digital/Multi-Media Card Host Controller Module
Full Chip Transistor-Level Post-layout simulation and Power analysis in Soc Design



