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NIV on full chip simulation of mixed signal designs


Liu YuanCheng
Leaguer Microelectronics Co.,Ltd.

Abstract

The paper discusses the importance for using NIV (Nanosim Integration with VCS) on full chip simulation of mixed-signal designs. It describes the methodology, strongpoint and detail implementation based on real design.

Key words

NIV; Mixed signal; Full chip simulation

1 Introduce

1.1 Verification requirement of Complex SOC design

Currently the miniaturization of electronics products become trend, especially the development of portable digital multimedia technology urges the system solution transfer from the muti-chips to single chip. The requirement of complex function on single chip became truth. It gives a new task to designer，that is how to do the full chip simulation for the mixed signal design to finish the completed function and parameter testing?

1.2 Design introduce

In the paper there is an example of mixed signal design to introduce the simulation requirement, the old and new simulation solution and describe the importance of NIV on full chip simulation of mixed signal design.

This design includes 3 analog blocks: PLL, Bias circuit, transmitter buffer and 1 digital processor block.

Figure 1: Block diagram of a mixed signal design

The main function of this design is that the digital block processes the data from the previous block and synchronized with the clock generated by the PLL of this design. The design gives differential output signal.
The expected input and output signal waveform is showed in figure 2.

Figure 2: expected input and output signal waveform

2 Design challenge

In our previous design flow, we use Star_sim/Star_simXT to do full chip simulation for our mixed signal design. The test vector which are generated by the digital simulation include an ideal clock defined in the verilog test bench, where all signal changes would be synchronous to this ideal clock. In fact, this clock is eventually from analog module PLL. During full chip simulation of mixed signal design what include user’s own PLL circuit, there is always a problem of synchronizing the simulation vectors. The test vector for digital core input is not synchronous with the actual PLL clock generated from the analog module PLL. This is because of the uncertainty of when the PLL would achieve lock. Due to this, it is always difficult to check the expected simulation result at the output ports of the chip.

Figure 3: the old full chip simulation flow

3 The new mixed signal SOC verification environment

3.1 NIV flow overview

NIV is a high-performance mixed-signal verification solution. It enables you to simulate transistor-level blocks written in NanoSim-supported transistor-level netlist (SPICE) files with digital blocks written in Verilog description files. NIV can accept any combination of many types’ netlist and models such as Verilog, Verilog-A, ADFMI and various SPICE (HSPICE, Spectre, Eldo, etc). It can also support post-layout back-annotation simulation. Fig.4 gives the basic NIV input/output description.

Fig.4 Input/Output of NIV

NIV supports both the Verilog-top and SPICE-top design flows. We can instantiate SPICE subcircuits in Verilog and/or instantiate Verilog modules in SPICE. As a result, a description using different views across different hierarchies may get a donuts configuration described as Fig. 5.

Fig. 5 The donuts configuration sketch map.

NIV supports the following features:

a) Verilog-top (SPICE-bottom/SPICE-Verilog doughnut) design flow

b) SPICE-top (Verilog-bottom/Verilog-SPICE doughnut) design flow

c) Multiple views

d) Automatic Verilog dummy module generation for SPICE subcircuit placeholders

e) Verilog-A Model instantiation

f) Hierarchical Verilog-A support

g) Cross-Module Reference (XMR) across the Verilog- SPICE boundary

In a given design, at a particular hierarchy, if more than one representation is available for simulation (from the choices of Verilog, SPICE, ADFMI, and Verilog-A), it is considered a multiple view. We can choose between the Verilog modules and SPICE subcircuits in a multiple view. We can choose either Verilog modules or SPICE subcircuits using the use_verilog (use_vcs) or use_spice (use_ns) mixed-signal simulation setup file commands.

Fig.6 gives the visual overview of the NIV flow.

Before simulation, the 1st thing is to determine if the design is SPICE-top or Verilog-top. Then, proceed as follows:

1). Prepare mixed-signal simulation setup file and the nanosim configuration file.
The default mixed-signal simulation setup file named vcsAD.ini. The mixed-signal simulation setup file contains all the information and file references needed to use NIV. It contains the choose command and many other optional commands. The choose command is used to point to NanoSim and its associated files.

The Nanosim configuration file contains all the specified nanosim commands for Nanosim verification.

2). Compile the design.

After all of the input files are prepared, the vcs command can be invoked using the following syntax:

vcs verilog_design_file(s) +ad [=simulation_setup_file] [vcs options]

It reads the default vcsAD.init file or the specifed setup file as the mixed-signal simulation setup file. The simv simulation executable is created (if no errors occur in the compilation).

3). Run your simulation.

After simv is generated (or another simulation executable file specified), the simulation can run using the following syntax:

simv [vcs run-time options]

4). Analyze the results.

In NIV, simulation results can be viewed separately with nWave or CosmosScope, which display the NanoSim output, or with VirSim, which displays the VCS output. Conversely, the output can be viewed by way of a single unified output display (UOD) file using nWave.

Fig. 6 Visual overview of NIV flow

Also, NIV can invoke from Composer through a graphic interface named Discovery AMS SimIF (Fig 7). The simulation interface can manage multiple tests under one project and include external digital libraries.

3.2 Benefits of NIV application on the design

we can integrate all of the digital and analog blocks in the verilog test bench. Nanosim will handle the spice netlist and any analog modules modeled using ADFMI C models, and VCS will take care of the verilog modules. The PLL clock output can now directly drive the digital circuit, so the test vector is always synchronous with the true PLL clock. Another advantage that we have found is that there is no need to convert the VCD file to VEC anymore. Furthermore, this flow also allows us to model some analog blocks using C models to speed up the mixed signal simulation.

Fig.7 Full chip simulation with NIV flow

Fig.8 and Fig.9 are the simulation result waveform with the old full chip simulation flow. Fig.8 shows that the PLL need a long time to lock the phase and become stable. But the test vector inputs from the simulation beginning, it is not synchronous with the PLL clock. Fig9 shows that when the PLL is stable all the digital and analog block work well, but we can’t check if the output data right. Because it is difficult to find out the relation between the input vector and output data, since the input vector is generated with an ideal clock in digital circuit simulation test bench.

Fig.8 Waveform 1 of full chip simulation result with old flow
Fig.9 Waveform 2 of full chip simulation result with old flow

Fig.10 is the simulation result waveform with the NIV full chip simulation flow. After the PLL become stable, the PLL output clock to drive the test bench to output the test vector, so it is very easy to check if the output is right by comparing with the input vector.

Fig.10 Waveform of full chip simulation result with NIV flow

4. Summary and expectation

Integrated mixed-signal IC design and verification environment is very helpful for today’s SOC designers to reduce design time and verification iterations. This article describes the NIV mixed-signal design flow based on a real design. The simulation results are compared with and without the NIV. According to the NIV simulation results, we achieve a good run time performance with satisfied accuracy.

The article just described some advantage for full chip simulation of mixed signal simulation with NIV flow, in fact, when you use it for your full chip simulation, you can find out more and more good feature. For example, for reducing the simulation time, you can use RTL or gate level netlist to replace the digital block, or you can use verilog-A model to replace the analog blocks. You can also set the spice simulation precision severally for the different analog blocks according to their different precision requirement.

I think in the future, the spice simulation with NIV will be speeded up with suitable precision. So we are preparing to do post-layout simulation with NIV next step.