The Application of PrimeRail for Dynamic IR-Drop Analysis In Godson-II Design
钟石强
中科院计算所
ABSTRACT
For most designs that use 90- and 65-nanometer process technologies, the analysis using a static approach is no longer sufficient and it becomes mandatory to analyze the actual variation of the supply voltage with respect to time for detecting chip failure conditions. PrimeRail is the key tool that can be used for gate-level and transistor-level Dynamic IR-Drop analysis.
This paper introduces the main design flow of PrimeRail and illustrates the application flow of PrimeRail used by ICT’ 90nm Godson-II design. Push a new way to realize the full-chip dynamic IR-Drop Analysis.
1.Introduction & background
Growing importance of voltage drop
The Above Diagram shows the emphasis of the growing impact of voltage-drop on delay. In nanometer designs, performance depends not only on input slope and output load, but also on interactions between nets and the growing influence of parasitic elements. Now, dynamic voltage drop effects are exacerbating the situation, contributing an estimated 10-15% delay in today’s 90nm designs.
Dynamic Voltage Drop and EM Analysis Is Now A Necessity
Dynamic voltage-drop is a growing challenge in today’s designs, thanks to advancements in process technologies and new design techniques. Wire resistance increases at 90nm and below, resulting in a significant increase in voltage drop: the actual voltage delivered to the transistors is significantly less than the supply voltage.
Moreover, in today’s low-power, high-performance designs, supply voltages continue to decrease (e.g. from 3.3V to 1.2V) while clock frequencies continue to increase (e.g. from 100 MHz to over 400 MHz). The compound effect is a severe reduction in the margin of error . For example, if the voltage delivered to the transistors drops by 150mV, the voltage drop is less than 5% of the 3.3V supply, but the same voltage-drop is equal to 12.5% for a 1.2V supply. To avert voltage-drop-related timing problems in 3.3V designs, a 10% noise-margin guard-band would suffice. However, in 1.2V designs, this 10% noise margin guard-band would prove insufficient to prevent performance degradation or functional failure.
In addition, current consumption in designs is also rising , In particular, transient current densities are increasing exponentially with increasing clock frequencies. This is resulting in higher power supply fluctuations and dynamic voltage-drop problems.
Godson-II Project adopts ST 90nm Process, The clock frequency is 1G.Hz For this project, it still can adopt AstroRail as before for full-chip static IR-Drop Analysis. But for the design at 90nm and below with high frequency (1GHz), just do Static IR-Drop analysis is insufficient. In order to prevent performance degradation or functional failure in Godson-II design, PrimeRail is used in this Project.
2. PrimeRail flow overview
Gate-level Static IR-Drop analysis
Transistor-level dynamic IR-Drop analysis
PrimeRail gate-level dynamic IR-Drop flow
PrimeRail is a sign-off power integrity tool. It is the key tool to finish gate-level dynamic-IR Drop analysis.
Gate-level dynamic IR-Drop flow includes 7 steps:
1) Design data setup for PrimeTime & PrimePower
2) Timing analysis by PrimeTime
3) Power analysis by PrimePower
4) Library characterization for intrinsic RC and current waveform tables
5) PG extraction
6) Current waveform generation
7) Rail analysis
For the gate-level dynamic IR-Drop analysis, we need use the synopsys tools: PrimRail, PrimePower, Hspice, Nanosim,StarRcxt and so on. Before the Gate-level dynamic IR-drop analysis, we need to run standard cell library characterization (the traditional standard cell library is not sufficient) , and also we need create hard-macro models for it.
3. Dynamic IR-Drop analysis for Godson-II Project
Godson-II Project use PrimeRail for Dymanic IR-Drop analysis.
Reference library preparation:
1) standard cell library characterization
The traditional standard cell library is insufficient for dynamic IR-Drop analysis. today’s library is based on energy for power models and do not have any information about current drawn at power and ground ports of each cell. This pre-characterization of the current wave-forms drawn at PG ports is important to speed-up the actual current-waveforms necessary for solving the voltage-drop. PrimeRail provides the capability to characterize the cells for each reference library. Current library characterization process in PrimeRail is a one-time process and involves two things: Intrinsic parasitic and current wave-froms generation.
● Create LM View
● Attach TLU+ model to reference library
● pgSpiceSetup setting the environment for RC extraction
and hspice simulation, using Hspice simulates in different simulation conditions.
● Intrinsic parasitics includes parasiti cresistance
and parasitic capacitance (generate .cin file).Base on the parasitic resistance and capacitance extracted before, Current waveform calculate the waveform according to the timing library (generate .cw file). link the characterization result to the reference library
● pgLinkCharacterize: read the .cin and .cw files in the standard cell library
● pgLinkpgSpec: link the power and ground to the
reference library.
2) Hard macro model Preparation
● Create CONN view
● Invoke command potxImporthardmacro “from_library” “to_library” “cell_name”, read in the hard macro transistor level result to the hard macro reference library
● pgExtraction: base on the CONN view, extraction Resistance and Capacitance from hard macro PG network
● pgSpiceSetup: RC extraction and nanosim post layout simulation environment setup
● pgLinkPgspec: Link power ground to the hard macro library
Godson-II Gate-level dynamic IR Drop analysis:
1) PrimePower power analysis
This Project uses StarRCxt for full-chip spef file extraction. VCD file is got from nc-verilog with 0-delay. In order to get saif file, we use PrimePower for it. In the PrimePower setting, using -vcd2saif in the calculate_power section. We can get the power result base on saif statistic toggle rate or dynamic power result base on the VCD.
In the Prime-power, set_waveform_options section, we should use the -interval option or -effort high for power calculating.
-interval options, less value of this made more bigger in the peak current. This result will effect the dynamic IR Drop analysis result
-effort high options, This is the parameter after prime Power 0506sp2 version. It can get the actual power result according to the delay calculated from the real design. In this Project, because we use the vcd file for simulation with 0-delay, This option have no effect.
Prime Power Result: The diagram below is used :
‘set_waveform_options ” .using option “interval”, The peak power is about 7.26w.
And the average power is 6.23w
Prime Power Result: The diagram below is used :
‘set_waveform_options ”.using option“effort high”, The peak power is about 417.8w.And the average power is 7.745w
2) PrimeRail power analysis
1） define poUseNewPowerDB 1
2） poLoadPowerSupply
setFormField “Load Power Supply” “TDF File Name” “power.tdf”
formOK “Load Power Supply”
3） poTransientPowerAnalysis “primerail_config.scr”
poTransientPowerAnalysis: can generate transient current waveform for the whole chip
when finish generating current waveform, can use poDumpPowerDBToFsdb “fileName.fsdb”dump power and ground current waveform according different cell_instance.
primerail_config.scr file format as follows:
Power_DB_Type : Deterministics
Power_Source : PrimePower
PrimePower_Analysis_Mode : Vectorbased
Simulation_Time_Interval : 15810001 5810020
Current_Waveform_Alignment_Mode : Start
Current_Waveform_Point_Number : 5
Prime_Power_Reports : saif.pp_power vcd.pp_power
3) PrimeRail dynamic IR_Drop analysis
1） poPGExtraction
setFormField “PG Net Extraction” “RC Extraction” “1″
setFormField “PG Net Extraction” “Reuse Old Extraction” “0″
formOK “PG Net Extraction”
2） poRailAnalysis
setFormField “P/G Rail Analysis” “File Name” “user_define.pad”
setFormField “P/G Rail Analysis” “Analysis Option” “Transient”
setFormField “P/G Rail Analysis” “Start Time”
“158.1e-4″
setFormField “P/G Rail Analysis” “End Time”
“158.101e-4″
setFormField “P/G Rail Analysis” “Transient waveform File“ “primerail_IR.fsdb”
setFormField “P/G Rail Analysis” “Res-Cur File” “primerail_IR.sp”
setFormField “P/G Rail Analysis” “Total Steps” “100″
setFormField “P/G Rail Analysis” “Step Size” “1e-9″
formOK “P/G Rail Analysis”
If we set the “define pgStatListSize 50”, we can got the maximum IR-Drop result lines.
4) Result of the analysis
Total power =9833mW(same as the prime power result comes from saif generating)
vdd max IR drop 77mv
max IR drop 44mv (center)
gnd max IR rise 176.153mv
max IR rise 46.28mv(center)
vdd max IR drop is 77mv，It is occurred at the corner near the center of the memory block. Pls see the diagram below: In the center of the chip, the maximum IR-Drop is 44mv
gnd max IR rise is 176.153mv, The position is same as the vdd，The IR rise of the center is 46.28mv
Put the PrimeRail power analysis result to the AstroRail, the result of IR_Drop is:
Total power =11W
Vdd max IR drop is 77mv
gnd max IR rise is 81mv
This maximum IR-Drop occurred in the center of the chip. AstroRail does not consider the effect of the internal power-rail of the memory block.
4. Conclusion
As a dynamic IR-Drop analysis tool, PrimeRail is very important for 90nm design. With the Godson-II Project, We familiar with this dynamic flow and prevent performance degradation or functional failure in our Project.
5. References
PrimeRail user Guide: Dynamic Analysis X-2005.09 September 2005, Synopsys Inc., U.S.A
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