2007-2008 年论文集

获一等奖论文

Speed Up Multi-Million SoC Implement Using Pilot Flow and IC

获二等奖论文

Synopsys Power-gating Design Methodology based on SMIC 90nm Process

HSIM^plus Based Custom AMS Solution Usage in High-Speed IC Interface Design

获三等奖论文

Verification of UniCore2-F64 using SystemVerilog and VMM

AMBA Bus Performance Test Based on PowerBench & SYNOPSYS’ VIP

IC Complier 在低功耗高性能设计中的应用

Improve ARM1176JZ-S Core Performance in a DCT+ICC flow
–Optimize timing and leakage power simultaneously at 65nm.

Multi-million Set-Top Box Static Timing Analysis using Distributed Multi-scenario Analysis

纪念奖论文

Using SystemVerilog Assertion to Verify the Constant Register Optimization

Advanced HSPICE Simulation and Cosmoscope Analysis techniques for High-speed I/O Design

Scan Fault Diagnosis and Physical Defect Identification

65nm L1 CACHE 宏单元的单元级再定制实现

DDR内存控制器时序收敛的物理设计

Improving SoC Development with Synopsys’ Verification Flow

新Galaxy 平台对面积和功耗的显著优化
——基于一款音视频处理芯片的实际应用

Integrate Custom Layout with IC Compiler Flow Based on 90nm Process

时钟产生模块的分支平衡设计