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Scan Fault Diagnosis and Physical Defect Identification


WANG Hong Wei
Design Center, STMicroelectronics R&D (Shenzhen) Co. Ltd.

Abstract

With an ever increased number of gate counts in a complex digital design, systematic and automatic methodology is required for design for testability. As the transistor numbers and metal layer go up in the design, the failure possibility is increasing during fabrication and packaging. Fault isolation technology becomes more critical in the DFT design.

Scan chains are a technique commonly used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. Based on the scan chains in digital design, Synopsys TetraMAX delivers the effective diagnosis and analysis features to help locate failures as precisely as possible. This method is widely used to optimize the manufacturing quality and save testing cost.

This paper introduces the DFT design flow for fault diagnosis with TetraMAX, and decrypts the failure isolation from fault candidates using ICWBEV and Hercules LVS feature. The example in the later part of this paper illustrates the methodology for detecting defects in one failure chip and verifies the feasibility of this diagnosis design flow.

Key Words: Fault Diagnosis, Scan Chain, DFT Design

INTRODUCTION

With the rapid development of semi-conductor industry and manufacture, more and more transistors have been integrated into an IC. Systematic and automatic DFT schemes should to be used for a larger and more complex digital design. Designers have been adopting ATPG based scan chains for detecting defects in logic core, and using BIST (Built-In-Self-Test) for locating defects in memories and hard macros. Using these methodologies, test engineers can achieve high test coverage, improve high test efficiency and save test costs. As the explosion of the transistor numbers per design and metal layers in sub-micron process, the failure possibility in a chip is increasing during product manufacturing and packaging.

Obviously, in high volume IC production process, it is very important for designers to find faults location rapidly and accurately. Locating faults has becoming critical challenges to help getting higher yield since the potential failures will propagate globally during the defects analysis. Failure diagnosis or analysis is a popular methodology to isolate suspecting faults as precisely as possible by physical defects identification for a design with scan chains. If the root of failures can be isolated, the appropriate design and manufacturing action can be taken for yield enhancement. In other words, failure diagnosis is not only used for locating chip failures, it can also be used for quality improvement.

There are two general diagnosis approaches. The first approach is to modify the scan structure to improve the diagnosis process, named as DFD (Design for Diagnosis, familiar to DFT design). In this approach some instances are added to increase the observer-ability and controllability. The second approach is to adopt ATPG patterns to diagnosis and to find the defect location by reading in the test patterns and monitoring the chip response. Since area and power consumption will be incremented in DFD design, the second approach with ATPG method is recommended and used popularly today.

A defect in a scan chain can cause wrong value to be captured into or shifted out a scan register. Synopsys TetraMAX provides an automatic analysis method to find out potential faults with the tester failure reports / information, by comparing the difference between the expected values and the found values during ATE testing. After designers invoke the diagnosis feature by executing “run diagnosis” command in TetraMAX, failure candidates are reported for the next deep analysis. Figure 1 indicates the ATPG diagnosis design flow in TetraMAX.

The following steps are recommended to diagnose the tester failure from log file in TetraMAX.

● Build up the ATPG environment for classical Single-Stuck-At model. Use the same configuration to the one used for pattern generation;

● Import the original patterns generated either by basic- scan patterns or fast-sequential patterns or both;

● Run diagnostic design flow by command “run diagnosis <failure file name -display>” or by ranking the failures candidates;

● Isolate the real faults from the failure candidates in chip, and analyze the cause to enhance the design or process;

Figure1.TetraMAX Pattern Generation and Failure Diagnosis Flow

DESIGN FLOW FOR DIAGNOSIS

Before running TetraMAX diagnosis flow, it is necessary for us to collect the failure information into a failure log file following the expected format. TetraMAX supports two types of failure log: pattern-based log or cycle-based log files.

During chip testing, ATE system can understand and analyze the test structure in the design database, i.e. scan chain architecture, mismatch DFF position and etc. By mapping to the classical information, the failing pins and failing cycles are reported for diagnosis analysis.

Failure log file usually is an ASCII test file, each line in the file describes a scan pattern mismatch happening between detected and expected values, the format shows as blow:

<pattern_num> <output_port> [cell_position] [expected/found]

pattern_num is the TetraMAX pattern number in which failure occurred, starting with 0 for the first pattern; output_port is the name of the output port where the failure is monitored; cell_position is the number of shift cycles which captures error data, and is used to determine the position of scan chain cell. Optional expected/found describes the expected value in pattern and the found value by ATE. Obviously, it is essential to make the correct association between failing vector and TetraMAX pattern when creating failure log file.

Here is a real fault diagnosis example. The failure log files were generated by tester Teradyne-Catalyst. Figure 2 illustrates the log file format. This log file includes all of the information, not only mismatch ports but also match ones. It is necessary to filter the unused information and translate them into TetraMAX accepted format.

Figure2.Failure Log File From Teradyne-Catalyst Tester

By using *.awk program, the ATE log file is translated into TetraMAX expected format, as shown in Figure 3. The assumption below was followed during log interpretation.

● A pattern is composed by a shift + capture procedure;

● Any failure during scan shift procedure belong to “pattern-1”, since those failures are relative to the shift in of previous pattern;

● Any failure during measurePO of capture procedure belong to current pattern;

Figure3.Failure Log File Adopting for TetraMAX after Conversion

Both pattern-based and cycle-based failure log files can be accepted by TetraMAX, and also the tool can rank the related scores for the collected failure candidates.

Based on the requirement, the script blow is used for the project faults diagnosis. Pattern-based failure log is used, and GUI interface is used to check failure instances (matching with the report list).

set messages log diagnosis_run.log -replace
report version -full

read netlist ../IMPORT/LIBRARY/IOCL_2V25MIN.v
read netlist ../IMPORT/LIBRARY/IOLIB_CL.v
read netlist ../IMPORT/LIBRARY/CORELIB.v

set build -black_box SP7D_4096×64m8
set build -black_box RO7A_28672×32m32_lsb
set build -black_box RO7A_28672×32m32_msb
set build -black_box SP7D_16384×24m32
set build -black_box SP7D_11264×24m32
set build -black_box SP7D_1024×24m8
set build -black_box RO7A_20480×24m32
set build -black_box SPS3_256×8m2d16
set build -black_box SPS3_1024×9m4d4

set build -black_box AF140
set build -black_box topPllPcm
set build -black_box OTP_10V_CL

read netlist ../IMPORT/NETLIST/top_sta016.v

run build_model top_sta016

run drc ../IMPORT/STIL/top_sta016.spf
run image image.dat -replace -violation

set patterns external ../IMPORT/PATTERN/sta016_pat_atpg.wgl

add faults -all
run diagnosis ../IMPORT/FAIL_LOG/failure_report.txt -display

Figure 4 shows the diagnosis reports with the tester failure log file. Generally, two possibilities happen during software analysis about imported patterns: explained ones and unexplained ones. With the explained patterns, the failure locations can be extracted from the verilog netlist and listed out. On the other hand, the unexplained pattern means that TetraMAX cannot map the relative failure logs into design architecture; this is possible because of the lack failure information (usually incomplete log transcription gotten with ATE limited memories) or software limitation (i.e. current TetraMAX can not explain the bridge and open faults etc.).

As for the physical defect location, there are two ways to locate the relative failure in layout according to your physical database types.
1. If post_layout Milkyway database is available, TetraMAX can use the data directly.
2. If only GDS layout is available, it is proposed to use the traditional design flow with ICWBEV.
In this paper, the second method is used because only GDS layout is available in this example.
Figure 5 indicates three possible areas for fault candidates’ identification with ATPG pattern.

Figure 4. Fault Diagnosis Results From TetraMAX
Figure5. Fault Candidates’ Identification Isolation with ICWBEV

By using the fault candidates’ list, the layer removal and step-by-step inspection are necessary to isolation real physical defect in failure chips with emission microscopy.

The observation result is that an abnormal emission spot was detected in DSP area, matching one of the possible failure locations calculated by using TetraMAX. Also after electrical operation, the weak oxide is found to be broken in DSP area and device was failed probably due to the damaged contact between the two metal metal5 strips induced by particle bridge melting. Figure 6 to figure 8 indicate the defects spots.

Figure 6.Failure Location Observed at Metal5 Layer
Figure 7.Two Parallel Metal5 Locally Melted Each Other
Figure 8.Damaged Oxide Observed After Metal Strips Removal

According to the analysis report of fabrication engineer, we found that the defects were caused by the bridge between two strips melted by the residual particle at metal layer 5. Luckily only small quantities of chips in the same volume production were found to have this kind of defects. The responsible engineers have improved the manufacturing environment for higher yield of this chip for future production.

Here is another example to locate defects in another fabricated IC based on MBIST diagnosis. We found that defects were due to a little mismatch between fabrication and RAM library which led to lower yield. We optimized the basic RAM cell by increasing the metal width of some of its interconnection wires and notch between 2-metals. As a result, the yield has been improved greatly.

Conclusion

As an effective faults diagnosis tool, TetraMAX diagnosis design flow can be used to diagnose and analyze manufacturing defects in an IC with various options, and detects the fault candidates list with ATE failure information. By isolating the fault candidates with emission microscopy, designers can identify the real physical defects. This failure information is useful and beneficial for yield improvement and the quality enhancement in chip manufacturing.

Reference

1. Synopsys: TetraMAX User Guide “Diagnosing Manufacturing Test Failures”;
2. Chris Eddleman etc.: “Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning”;
3. Chia Ling Kong etc.: “Diagnosis of Multiple Scan Chain Faults”;
4. STMicroelectronics: “ATPG for Failure Diagnosis Application Notes”;