Synopsys Power-gating Design Methodology based on SMIC 90nm Process

Eugene Wang
Semiconductor Manufacturing International Corporation (SMIC)

Abstract

Power consumption has always been a big issue for portable application. In today’s rapid growing technology world, multi-media and diversified functions were incorporated into portable devices have made power consumption a further challenge. Either battery’s lifetime has to be prolonged or architecture of the design needs to be remodeled. This paper, however, will focus on implementation of low power design with Synopsys low power solution. It will highlight leakage power reduction through power-gating technique. The suggested method has been achieved based on ARM’s library for SMIC (Semiconductor Manufacturing International Corporation) 90nm process. This paper first illustrates leakage control theory. Then, it explores the concept of power-gating. Finally, it discussed advanced power-gating design methodology from RTL to verified GDSII. This paper is written based on SMIC-Synopsys Reference Flow 3.2 anchored by Synopsys Galaxy implementation platform and Discovery verification platform.

Keywords: 90nm, leakage power, power-gating, Reference Flow, SMIC, Synopsys

1.0 Introduction

As we entered into deep sub-micron process, down scaling of geometry size made current density substantial. Power dissipation raises. Designers tend to lower supply voltage to reduce the overall power consumption and yet, this leads to performance weakening. By utilizing low threshold voltage (Vth) devices, designers are able to alleviate performance degradation but at the expense of leakage power. This shows that there is never a win-win solution in semiconductor field. The solution to this problem may become the problem of the next. Designers are often facing problems to balance tradeoffs between different design aspects. Up to a few years back, leakage power was still tolerable. Now it has turned into a significant factor that cannot be neglected. In fact, leakage power increases exponentially as technology scales downward. This paper will use ARM library for SMIC 90nm process to demonstrate how leakage power can be handled during design flow from RTL to GDSII.

2.0 Leakage Current Control Theory

Leakage power arises whenever there is leakage current flow during standby mode. In CMOS (Complementary Metal-Oxide Semiconductor) technology, leakage current has many different components. Yet, the biggest portion comes from sub-threshold leakage current. Sub-threshold leakage current is, in fact, drain-to-source current flows in the channel of a MOS device in the weak inversion region in which the diffusion current is caused by the minority carriers. For example, when a low input voltage is applied to an inverter, a high voltage potential is observed at its output terminal. In theory, PMOS is switched on and NMOS is switched off. In reality, NMOS is not completely shut-off; there is still a leakage current flowing in its channel due to the VDD potential of VDS. This leakage current can be expressed by the following equation [1].

where IDS is the drain to source current; VDS is the drain to source voltage; VT is the threshold voltage; VGS is the transistor gate to source voltage; K and n are functions of technology, andηis the drain-induced barrier lowering (DIBL) coefficient. VT plays an important role in this equation. The increase of VT means the reduction of leakage current exponentially. However, the increase of threshold voltage also means the delay of switching on and off of MOS device. To some extent, this technique is still feasible in the CMOS technology. Nevertheless, if one takes a closer look at the above equation, one can also reduce leakage current by lowering VGS (transistor gate to source voltage). A clear picture is shown below by plotting the above equation, assuming a constant drain to source voltage and zero body to source voltage [1].

This graph shows that gate to source voltage increases exponentially with drain current. As a result, decreasing the transistor gate to source voltage will greatly reduce the leakage current and hence leakage power. This is the principle that the paper is based on to discuss the concept of power-gating in the next chapter.

3.0 Concept of Power-gating

Figure 1. Fine-grain power-gating with inverter

Power-gating reduces leakage by reducing transistor gate to source voltage. The operation of power-gating technique is simple. A header (p-type transistor) switch is placed in between a block and power to control supply power from this block with sleep signal (Please refer to Figure 1). In active mode, virtual voltage (VVDD) is acting as power supply at a potential of approximately VDD to the block; leakage power exists both in header and this circuit block. In standby mode, header is switched off, meaning that virtual voltage is beginning to drop with time. Virtual voltage is no longer at VDD, but rather at a voltage somewhat above VSS at saturation point. Hence, transistor gate to source voltage is reduced. As soon as virtual voltage starts to fall, leakage power saving in this block begins. Yet, leakage still exists in the header. This is why sleep transistors are usually made of high threshold voltage (Vth) devices to prevent from cell leakage while maintaining a high potential at virtual rail. This combination of using high Vth headers and low Vth standard cells are called MTCMOS (Multi-Threshold CMOS). Same principle applies to a footer (n-type transistor) switch where it is inserted between a block and ground. Both headers and footers are employed alternatively in a power-gating design. The analysis of timing delay and power consumption for this approach is simple since library vendors usually incorporate sleep transistors as part of the standard cells. The delay and power consumption are reported together with sleep transistors in Liberty file. Nevertheless, the parameter such as the size of header/footer cells to drive the logic block is restricted. The distribution of global sleep control signal to every single cell is a challenge part that makes the implementation difficult. Area penalty is another factor that constitutes its flaw. Since every standard cells are tagged to an additional transistor, chip area employing this library will be much bigger than a normal one. This will result a larger die size on wafer and leads to cost increasing. It is also required a set of libraries (libraries of high VT, low VT with sleep transistors and a normal library without sleep transistors) for a well power saving, timing closure and area efficiency design. This indeed augments library vendors’ burden. This type of power-gating is known as fine-grain power-gating [2].

A coarse-grain power-gating is similar to fine-grain power-gating, but these sleep transistors are coarsely placed throughout the chip. It does not need a whole set of new library, but some power management cells such as headers and footers. Unlike fine-grain power-gating, coarse-grain approach does not rely wholly on the quality of library, but mostly the capability of how EDA tools handle. A set of p-type transistors is distributed inside a voltage area to control the power supply of this region, which is designed to power off (please refer to Figure 2). The operation of coarse-grain power-gating is same as that of fine-grain power-gating. However, the implementation and analysis behind this mechanism is quite complex. The size and numbers of sleep transistors to be placed inside the power off voltage area are now parameters to

Figure 2. Coarse-grain power-gating

control the driving capability to this region. This will lead to IR (voltage) drop variation and performance regression. When all header switches are turned back on simultaneously, there is a instantaneous charging/discharging current and short-circuit current flowing from VDD to VSS. The aggregate current is known as power-up rush current. This current needs to be study carefully to avoid device malfunction or potential chip failure. This is the major concern in coarse-grain power-gating implementation. Wake-up time is another key factor in the analysis flow of a power-gating design. It is refered to as the time it takes for VVDD to reach to VDD so that devices inside the shutdown region can be function ready. These complex methodologies and analysis are discussed in the next chapter [2].

4.0 Power-gating Design Methodology

In this chapter, we will use a simple test case to demonstrate a coarse-grain power-gating methodology. This design methodology from RTL to GDSII can be break down into five sections: power-gating aware simulation, RTL synthesis, floorplan, physical optimization and dynamic IR drop analysis. In the first section, low power simulation is done in Synopsys VCS where power behavior is observed. Section 2 will discuss synthesis scripts regarding to power-gating flow. Section 3 and 4 will explain back-end implementation concerns of coarse-grain power-gating technique in Synopsys IC Compiler. Finally, section 5 will discuss Synopsys advanced dynamic power analysis in PrimeRail. IR drop, power-up rush current and wake-up time analysis will be illustrated with examples.

Figure 3. Synopsys power-gating design methodology

4.1 Design overview

The testcase that is demonstrated in this paper is a block-level design called des_hard_macro shown in Figure 4. In this design, we create two power domains: shutdown and regular. Shutdown domain is on the left hand side of the diagram where u_des_hard_macro_core is observed; regular domain is located on the right hand side of diagram where u_des_hard_macro_bypass is. Both power domains are operated in 1.2V. Nevertheless, u_des_hard_macro_core can be power off whenever signal pg_en is set to logic high. Retention registers (RR) and isolation cells (ISO) are required to place throughout the chip to control the data retain and data isolation when the block is power off. Therefore, there are three key control signals, pg_en, retain_n and iso_en_n. These three control signals are essential in the simulation stage which will be discussed in the next section.

Figure 4. des_hard_macro diagram

4.2 Power-gating aware simulation

Before digging into power-gating design flow implementation, one needs to verify his design’s functionality and ensure correct operation of power behavior. Synopsys power system task (verilog/VHDL) offers the capability to perform low power simulation with Synopsys VCS in RTL level. The verilog system task coding are $power and $isolate. In RTL netlist, users need to describe shutdown domain’s behavior through $power; such as control signal active/inactive sense, power domain name, instance name, etc. Users also have to illustrate connectivity between shutdown domain and regular domain through $isolate. This includes isolation cells’ input/output signals, control signals and clamp signals. (Clamp signals refer to as the output logic state when shutdown domain is power off)
After $power and $isolate are specified in RTL netlist, the VCS command can be invoked using the following syntax:

% unix> vcs –power_aware [vcs options]

For the following paragraph, please refer to Figure 5 & 6 for a better illustration (A graphic plot of our simulation result is shown in Figure 5 and power shutdown diagram is shown in Figure 6). The procedure of power shutdown begins with iso_en_n signal. When iso_en_n is asserted, the output signal (i_rdata_core) from ISO into the regular domain is logic 0. This was defined in RTL code through $isolate. ($isolate (rdata_core, iso_en_n, rdata_core_mv, 8’b0);) During power off mode (pg_en enable), the output signal of the shutdown block is observed unknown state, which shows X on the picture below. The data was not retained at this time. The inputs (o_tdata_core and i_rdata) to the shutdown region still maintain at its original state (Note that input signal is not required to be isolated.) During power on mode (pg_en disable), a reset_n signal is asserted to initialize design. Finally, iso_en_n is de-asserted [3].

Figure 5. des_hard_macro simulation results

Figure 6. Power shutdown diagram

As shown in the above simulation result, we can easily portray power intent of our design through Synopsys VCS simulator. In a more complex design, data retain, data isolate and power behavior need to be carefully studied in order to ensure a proper operation. With Synopsys power system task, we can anticipate a successful operation of low power design as early as in RTL stage. Then, we can move on to the next step, RTL synthesis.

4.3 RTL synthesis

Front-end designers must be aware of power information in synthesis stage. In particular, the following shows the necessary steps for a power-gating design in RTL synthesis phase. This part was done in Synopsys Design Compiler.

Figure 7. RTL synthesis sub-flow

4.3.1 Power domain creation

Designers must create power domain as early as in synthesis stage. The purpose is to group hierarchical logic information that share the following [4]:
• Primary voltage states or voltage range (that is, the same operating voltage)
• Power net hookup requirements
• Power-down control and acknowledge signals (if any)
• Power switching style
• Same process, voltage, and temperature (PVT) operating condition values (all cells of the power domain except level shifters)
• Same set or subset of nonlinear delay model (NLDM) target libraries
Design Compiler will translate $power which is specified in RTL code into equivalent power domain through infer_power_domain command. In the case that designers want to define power domain manually, please refer to the following example. For shutdown domain, users need to specify its primary power/ground, backup power/ground (for contributing power to always-on cells placed inside the shutdown region during power off mode) and internal power/ground. The following is an example that was used in SMIC-Synopsys Reference Flow.
create_power_net_info VVDD -power
…
connect_power_domain core_pd \
-primary_power_net VDD \
-backup_power_net VDD \
-internal_power_net VVDD \
-primary_ground_net VS

Figure 8. Power domain creation

4.3.2 Isolation cell mapping

Isolation cell mapping is done automatically in Design Compiler because $isolate construct has been declared in RTL netlist. During synthesis phase, $isolate is first translated into isolation cell of GTECH library. Then GTECH_ISO is mapped into isolation cell of synthesis library. Nevertheless, Design Compiler inserts ISO cell regardless of its output signal’s connectivity. That is, one may discover that ISO cell output signal is floating. To avoid such a problem, designers need to verify ISO output signals’ net and see whether or not they are connected. In the reference flow, we introduce a simple tcl script to remove redundant ISO cell.

4.3.3 Retention register mapping

Retention registers are required when the data inside the shutdown region is to be preserved so that next time when the block is back online, everything can function properly. Designers must be well aware of the specific registers that need to be swapped to retention registers to meet power intent requirement. This is done in Design Compiler with one pass power gating flow. It basically removes the need of compile incremental and simplifies the UI. The related commands are power_enable_one_pass_power_gating, set_power_gating_style, set_power_gating_signal, hookup_power_gating_ports. The following shows an example of how to perform one pass power gating flow.

set_ideal_network retain_n
set power_enable_one_pass_power_gating true
current_design des_hard_macro_core
set_power_gating_style -type DRFF [get_cells pair_0__u_01/*kdin_reg*]
set_power_gating_signal -type DRFF -power_pin_index 1 [get_port retain_n]
hookup_power_gating_ports -type DRFF -port_naming_style {RETN}
compil

Figure 9. Retention register mapping

4.4 Floorplan

In this section, we will discuss floorplan related concerns of a power-gating design. This part was done in Synopsys IC Compiler. Floorplan sub-flow is shown below.

Figure 10. Floorplan sub-flow

4.4.1 Create voltage area

In a multiple voltage design implementation, designers are able to create placement constraints for cells that are related within the region. The purpose is to set up perimeters for cells that are corresponded with its logic information which was previously defined by power domain creation (section 4.3.1). When create_voltage_area command is defined, during place_opt step, IC Compiler will place all the cells associated with voltage area within its geometrical boundary and all the other cells outside. In this case, u_des_hard_macro_core module will be placed inside the voltage area.

4.4.2 Power-gating cell array placement

Power-gating design implementation can be achieved by either headers or footers, or by both header and footer cells in an alternating fashion. In this sub-section, we will use headers to demonstrate power-gating placement. The related syntax is: add_header_footer_cell_array [options]
In our design, HEADBUF64M was used to distribute evenly throughout the voltage area “core_pd”. The size of power-gating cells, which determines the driving strength that drives the virtual voltage of its neighboring cells, has a big impact on IR (voltage) drop variation. Moreover, the distance that separates each header cell plays an important role in the power network integrity. These design aspects have to be carefully studied in the early stage of back-end implementation flow. Rule of thumb is the larger the size of power-gating cells, the smaller the IR drop is. Yet, the greater the rush current will be. Synopsys power network analysis (PNA) is able to give a rough estimation of IR drop and peak current as early as in floorplan stage. It will be explained in section 4.4.5. Below shows the header cells array placement that was done in [3].

Figure 11. header cells array placement

4.4.3 PG net connectivity

Power and ground nets need to be connected logically in accordance to its physical PG connection. It has to be done before physically PG connection. In this design, because we are using header cells to power off the shutdown region, there are total of three PG nets, namely VVDD, VDD and VSS. In fact, VVDD (virtual VDD) net is the primary power rail that lies inside the voltage area. Therefore, VVDD net is also called an internal power net that is connected to the standard cells’ pin (VDD) inside the voltage area. Power management (PM) cells, which are placed inside the voltage area, need to be connected to global VDD (VDD) so that they will not be power off during standby mode. Hence, VDD net is connected to PM cells’ pin (VDDG). ARM library for SMIC 90nm process offer the capability to support both shutdown of PM cells. Hence, designers can utilize header cells to power-gate shutdown cells or footer cells to ground-gate shutdown cells. Always-on cells and retention registers also have both VDDG and VSSG pins for both PM cells implementation. As a result, it is required to do PG connect for VDDG pins and VSSG pins of these special cells. Finally, VDD and VSS nets are connected to the standard cells’ pin VDD and VSS respectively in the default region. Below shows an example of PG connect script and the schematic PG pins of special cells.

connect_pg_nets -nets VDD -ports VDDG -net_type power -mode connect -voltage_area core_p

Figure 12. Logic P/G connect script

Figure 13. Always-on cell Figure 14. Header cell Figure 15. Footer cell Figure 16. Retention register

4.4.4 Power planning

Power planning has a direct impact on the whole chip power integrity. It requires a lot of manual and iterative works. Designers need to calculate the width and the number of power straps very carefully in order to meet IR drop constraint while minimizing routing resource. In des_hard_macro design, there are virtual VVDD, real VDD and VSS network. It is suggested to place global VDD power straps close to header cells in the power off region to avoid long wire connection in power-gating secondary pin preroute.
Below shows the power network structure of des_hard_macro design.

Figure 17. des_hard_macro VVDD Figure 18. des_hard_macro VDD Figure 19. des_hard_macro VSS

4.4.5 Power network analysis

Synopsys power network analysis (PNA) offers an early IR drop analysis on specific power domain. It gives engineers a rough estimation of the chip IR drop and peak current. If the results are not satisfied, designers can simply go back to power planning stage to modify their power network accordingly. This is indeed helpful because it greatly reduces a big design cycle if the IR drop result is unsatisfied at signoff phase. With user-defined power budget for the chip, PNA is able to plot IR drop map. For a power-gating implementation, channel resistance of power-gating cells is needed to estimate IR drop. Channel resistance can be calculated with library characterization in PrimeRail in section 4.6.1.1. In our case, the results are shown below.
Maximum IR drop in des_hard_macro: 7.07 mV
Maximum current in des_hard_macro: 2.218 mA

Figure 20. des_hard_macro IR drop map

The red color on the above map shows the peak IR drop value, 7.07 mV, which covers part of the voltage area, core_pd; however, this value, 7.07 mV is 0.6% of the supply voltage, 1.2V [5]. If the analysis results from Synopsys PNA lie within user-defined target margin, we will perform power-gating secondary pin connection since the location and size of header cells will not change anymore. This task will connect physically VDDG pins on header cells to VDD power network [3]. Below shows a snapshot of PM cell secondary PG pin preroute.

Figure 21. Power-gating secondary PG pin preroute

4.5 Physical optimization

Physical synthesis for a power-gating implementation is also done in Synopsys IC Compiler. In general, there are two issues to be aware of: power-gating control signal connectivity and always-on network synthesis. Below shows the sub-flow.

Figure 22. Physical optimization sub-flow

4.5.1 Power-gating control signal connectivity

Power-gating control signal holds the key factor that impacts chip performance. In the worse case scenario where all power-gating cells switched on simultaneously, instant rush current flowing into the channel of transistors will damage the device. To prevent this issue, a daisy chain mechanism is used. By chaining the gate control buffers of power-gating cells, a nature delay in propagating control signal will switch on power-gating cell one after another. As a result, rush current can be mitigated. The actual IR drop value and rush current analysis is performed in Synopsys PrimeRail, which will be discussed in section 4.6. Below shows daisy-chain snapshot and a close-up look.

Figure 23. Daisy-chaining power-gating cells snapshot

Figure 24. Close-up look of daisy-chaining power-gating cells

4.5.2 Always-on network synthesis

Always-on synthesis is applied only to a power off region where certain cells are remained function during standby mode. Nets that are connected to these cells must be synthesized with always-on network strategy. In general, there are three types of always-on network. The first one is control signal of retention registers. It is part of the always-on network since certain data needs to be retained during standby mode and restored during active mode. Control signal must be always on in order to preserve such an operation. The second one is the switch enable signal of power-gating cells. It is required to have always-on net for this switch enable signal to manage the power behavior of shutdown region. The last one is feedthrough always-on net where signal net passes across shutdown area. When a feedthrough wire is too long, it is possible that tool will insert buffers/inverters for this net. However, these discussed feedthrough signals are belong to default (always-on) region. Therefore, we have to perform always-on network synthesis to avoid potential issues that may occur in the circumstances mentioned above. Always-on network strategy specifies the types of cells are to be used for always-on repeater. Designers can choose to use dual power/ground cells in which backup supply (VDDG/VSSG) is connected to, or single power type with special location reserved for always-on region. In this design, we use a dual power type always-on strategy [5]. First, always-on cells must be available to use (i.e. set dont_touch false). Second, always-on attribute is set to true if they are not defined in Liberty file. Then after enabling always-on synthesis (set enable_ao_synthesis true), we can set always-on strategy (set_always_on_strategy) to either dual power or single power type. Finally, place_opt will place always-on cells in the appropriate places.

Figure 25. Always-on synthesis snapshot

4.5.3 Always-on cells & retention registers secondary PG pin preroute

When always-on cells and retention registers are in-placed, we have to connect their power/ground secondary pins to corresponding supply network. This task is similar to PM cell secondary PG pin preroute but both VDDG and VSSG pins of always-on cells and retention registers must be connected. It is essential to first perform PG pins logic connect before connect them physically. Below shows a snapshot of secondary PG pin preroute.

Figure 26. Secondary pin preroute snapshot

4.6 Dynamic IR drop analysis

To ensure an actual timing closure of power-gating design, one has to first take the detail transient power analysis to observe the IR drop value and evaluate if it falls beneath the range of cell-library characterization limits. This analysis is done in cell level with Synopsys PrimeTime-PX and PrimeRail for a signoff power analysis. In this section, dynamic rail analysis, power-up rush current and wake-up time analysis are discussed.

4.6.1 Dynamic rail analysis

In this sub-section, IR drop value will be calculated. Below shows the dynamic rail analysis flow.

Figure 27. Dynamic rail analysis flow

4.6.1.1 Library characterization

Traditional timing/power models are insufficient for dynamic power analysis since they do not take into account of the effect of intrinsic parasitics and do not have detailed view of current drawn from power supply network to each power/ground ports of the instances. Therefore, in order to perform dynamic power analysis, we first have to model accurately two data: intrinsic parasitic of RC and detailed dynamic current waveform. Unless CCS power model is available, this step is done in PrimeRail with HSPICE engine [6].
In general, there are four types of characterization options shown below:
Intrinsic parasitic
Intrinsic parasitic contributes a significant portion to the total capacitive loading of the power supply network seen in a CMOS circuit [6]. Since current is drawn from the power supply terminal to the load, the effects of intrinsic parasitic have to take into consideration. These effects are state-dependent [6]. Please refer to the figure below.

Figure 28. Intrinsic parasitic effects

Current waveform

PrimeRail will model detailed current waveform drawn from the power supply network to the cell. This waveform is similar to the table lookup power models that are described in the Liberty file. However, this detailed current waveform is not only a function of input slew and output load capacitance, but for a given switching event, the trip points of such a waveform are captured [6]. (i.e. they’re also time-dependent.)

Figure 29 Characterization circuit structure and current waveform captured

Filler cell leakage current

If the IR drop values are beyond the boundary of design requirement, PrimeRail is capable to reduce IR drop by inserting decoupled capacitance. Nonetheless, inserting decoupled capacitance induces leakage power. To analyze the effect of leakage power brought by decoupled capacitance, we have to first use PrimeRail to model the leakage current of filler cells in the library characterization stage [6].

Power management cells

It is required to model power management cells for a power-gating design in order to analyze the effect of rush current and wake-up time. Fundamentally, PrimeRail uses SPICE netlist together with HSPICE to generate IV curve characteristics. Users need to define PM cell’s statement such as the conditions to switch on/off PM cells and the control signal in the P/G spec file [6].
The prerequisite for running library characterization are shown below [6].
• Have Spice models.
• Access to Spice binary and able to execute.
• Liberty models (LM view) attached to the library.
• Have power and ground ports specification file ready.
• Have circuit description language (cdl) netlist with power and ground port declared at subckt port list.
• Milkyway reference library opened.
After library characterization, intrinsic parasitics (*.cin), current waveforms (*.cw), filler cell leakage current (*.fc) and PM cell (*.pm) data will be generated. Note that different types of cells, different characterization options need to be selected. After PM cell characterization, one should be able to observe linear (channel) resistance result in PrimeRail log file. (This channel resistance result needs to be specified in PNA in order to anticipate IR drop in floorplan stage)

4.6.1.2 Power analysis in PrimeTime-PX

PrimeRail does not perform power analysis; rather it takes the results from either Power Compiler or PrimePower or PrimeTime-PX. In this case, we utilize PrimeTime-PX for this analysis flow. Switching activity for each of registers gate input, output and clock pins are estimated for a vector-less approach. One key variable to notice is power_rail_output_file. PrimeTime will generate a binary power report file based on the filename that is specified by users to this variable. This binary power report file will be fed into PrimeRail to perform further analysis.

4.6.1.3 PG extraction

Perform dynamic power analysis at cell level requires extracting both resistance and capacitance of power and ground network. PrimeRail will extract RC values of power and ground network based on TLU+ model. Both global VDD and virtual VDD RC values will need to be extracted [6].

4.6.1.4 Power analysis

PrimeRail uses previously characterized data (library characterization) and PrimeTime binary power report file to generate dynamic current waveform stored as RAIL view in the design library. This RAIL view will be referenced later in rail analysis. In this case, we use time-average-based analysis (vector-free). PrimeRail supports the statistical analysis based on the time-average switching behavior of the circuit for a single clock period [6]. Related command: poTransientPowerAnalysis

4.6.1.5 Rail analysis

PrimeRail will use the resulted RAIL view to perform rail analysis with the command poRailAnalysis “dynamic“

Figure 30. Rail analysis

Select “combined mode” to analyze power network of both VDD and VVDD.
For chip-level rail analysis, top-level design pad instance or master name has to be specified. In this case, we use “use top-level design pin as pad” for a block-level rail analysis [6].

4.6.1.6 Display & report

Rail analysis results are stored back in RAIL view in the design library. Users can display the results with pgMap command. Peak IR drop, average IR drop, resistivity-map can be displayed graphically based on specified power network. IR drop values are shown in the log file. In this log file shown below, the peak IR drop value for VDD + VVDD network is 100.664 mV (sum of VDD IR drop, 42.002 and VVDD IR drop, 58.662), which is approx. 8.4% of supply voltage 1.2V. The average IR drop value is 7.134 mV, which is very close to the estimated value in PNA result. VSS IR rise, in this case, are quite small compared to VDD IR drop values. One of the advantages that PrimeRail has is that users are able to view rail analysis results next time in PrimeRail as long as RAIL view exists and intact.
Power domain VDD network voltage report
PEAK transient voltage:
Min voltage rise (mV) = 0
Max voltage rise (mV) = 0
Min voltage drop (mV) = 0
Max voltage drop (mV) = 42.002
AVG transient voltage:
Min voltage drop (mV) = 0
Max voltage drop (mV) = 3.132
Power domain VVDD network voltage report
PEAK transient voltage:
Min voltage rise (mV) = 0
Max voltage rise (mV) = 0
Min voltage drop (mV) = 44.565
Max voltage drop (mV) = 58.662
AVG transient voltage:
Min voltage drop (mV) = 3.433
Max voltage drop (mV) = 4.002 Power domain VSS network voltage report
PEAK transient voltage:
Min voltage rise (mV) = 0
Max voltage rise (mV) = 32.304
Min voltage drop (mV) = 0
Max voltage drop (mV) = 0
AVG transient voltage:
Min voltage rise (mV) = 0
Max voltage rise (mV) = 2.021

Figure 31. Rail analysis results shown in log file

Figure 32. VDD + VVDD peak IR drop map

Figure 33. VSS peak IR rise map

4.6.2 Power-up rush current and wake-up time analysis

In this sub-section, rush current and wake-up time is estimated in PrimeRail. It is suggested to run this flow on a different database than the one in dynamic rail analysis flow.

Figure 34. Rush current & wake-up time analysis flow

4.6.2.1 PM cell characterization

Similar to section 4.6.1.1.

4.6.2.2 PG extraction

Similar to section 4.6.1.3.

4.6.2.3 Power analysis to generate PM cell event data

Instead of having users to describe power-gating cells’ event information, PrimeRail is able to generate them for you. This event data is of an ASCII format. Users are able to change the content of this file to perform what-if analysis. The procedure is follows,<1> Users need define a variable, poDumpVFPMCellEvent , through scheme command. In order for this variable to be effective, poTransientPowerAnalysis must be run twice: First time with “Vector-free” mode; second time with “Assign Only” mode.
<2> Run poTransientPowerAnalysis for the first time, with “Vector-free” mode. (Section 4.6.1.4)
<3> Run poTransientPowerAnalysis for the second time, with “Assign Only” mode.
<4> PM cell event data generated.
scheme { define poDumpVFPMCellEvent “des_hard_macro.power_up_event.data” }
poTransientPowerAnalysis ## Run for the first time
setFormField “Transient Power Analysis” “Power Analysis Mode” “Vector-free”
formOK “Transient Power Analysis”
poTransientPowerAnalysis ## Run for the second time
setFormField “Transient Power Analysis” “Power Analysis Mode” “Assign Only”
setFormField “Transient Power Analysis” “Current Waveform File” “des_hard_macro.power_up_event.data”
formOK “Transient Power Analysis”

Figure 35. PM cell event data generation example

4.6.2.4 Rail analysis with PM cell event data

In order to turn on power-up analysis mode, a PM configuration file needs to be define through pgPMConfigFile

scheme { define pgPMConfigFile “des_hard_macro.pm_rail_analysis.cfg” }

Figure 36. Define pgPMConfigFile

The content of config file can leave it as default values shown below [6]. Notice that event filename is specified in this config file.
# Power Management Control File
# First word is KEY word
# lines which starts with # are treated as comments
# Threshold 0.01
# MaxSteps 100000
StepSize 1.0e-12
MaxCurrentFile des_hard_macro.maxcurrent.out
Current_Waveform_File des_hard_macro.power_up_event.data
SaveStdCellVoltage true
Dump des_hard_macro.pm_dump.out
Threshold 0.01

Figure 37. des_hard_macro.pm_rail_analysis.cfg

Then poRailAnalysis “dynamic“ is performed. (Please refer to section 4.6.1.5)
The report is shown in PrimeRail log file. In this demo test case, we used a total of 315 PM cells to control 19448 standard cells. Total power off leakage were considered only PM cells. Power-up rush current is 47.335mA occurred at 8.17ns and wake-up time for devices inside power off region to reach stable voltage 1.188V is 11.254ns.
Power Management Analysis Report
Controlled voltage domain 1: VVDD
315 power management cell channels are used to control 19448 std cells.
Total OFF leakage current from PM cells is 24.443e-3 (uA).
Total ON leakage current from std cells is 9.018 (uA).
0% (3.502329e3) 10% 20% 30% 40% 50% (7.606532e3) 60% 70% 80% 90% (9.60019e3)
Stable PG net voltage 1.188 (V) is reached at wakeup time 11.254e3 [ start at 3.42e3 duration 7.835e3 ] (ps).
Peak current 47.335e-3 (A) is required at 8.17e3 (ps).
Max voltage difference 1.188e3 (mV) occurs at 11.254e3 (ps).

Figure 38. Rush-current & wake-up time report

5.0 Conclusion

This paper has demonstrated Synopsys design methodology to minimize leakage power through power-gating implementation. This prevailing technique has been achieved using ARM’s library for SMIC 90nm process in SMIC-Synopsys Reference Flow 3.2 project. Although Synopsys now uses UPF (Unified Power Format) language to describe the power intent of the design, the principle remains the same as discussed in this paper. Indeed, the emerging of power-gating has significantly reduced chip’s leakage power. Yet, the amount of leakage saving during standby mode period vs. the amount of power loss in power-gating transistors during power-up are remained to designers to tradeoff.

6.0 Acknowledgments

The author would like to give his sincere gratitude to colleagues in SMIC design service teams for their kind support. Special thanks dedicated to Synopsys’s Wendy Chen and Chris Zhou for their valuable contribution to this paper and SMIC-Synopsys Reference Flow 3.2.

Reference

[1] Abdollahi, A., Fallah, F., Pedram, M., “Leakage current reduction in CMOS VLSI circuits by input vector control,” IEEE Trans. on VLSI Systems, Vol. 12, No. 2, Feb. 2004, pp. 140-154.
[2] Frenkil, J., Venkatraman, S., “Power-gating Design Automation,” chapter 10, “Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design,” No.1, 2007
[3] SMIC-Synopsys Reference Flow 3.2 manual, October 2007, SMIC.
[4] Design Compiler User Guide, version Z-2007.03, March 2007, Synopsys.
[5] IC Compiler User Guide, version A-2007.12, December 2007, Synopsys.
[6] PrimeRail User Guide: Dynamic Analysis, version Z-2007.03, March 2007, Synopsys.

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