Abstract

Modern deep-submicron microelectronic technologies make semiconductor integration reach great degrees. But such integration results in a crucial issue for the whole chip verification. The complexity of circuitry and model compels designer to find a verification solution with well situated accuracy and acceptable speed. Our high speed development team has been suggested to use a fast-spice mixed-signal simulation solution, the XA-VCS, to verify our multi-channel IO interface chip. We performed about 40 mixed-signal test cases to verify the whole chip function with XA-VCS. During pre-layout and post-layout simulation with various testcases, XA-VCS shows typically about 10 times speed acceleration than our previous Nanosim-VCS co-sim solution, which makes sure to meet our limited verification schedule. This paper introduces the XA-VCS environment configuration and simulation result on a 2.5G multi-channel SERDES testcase. The contrast with traditional Fast-Spice simulation solution such as Nanosim-VCS is also listed. To satisfy mixed-signal full chip verification, we think there are some desired features to be improved. It has been described in this paper also.

1. Introduction: our project background

This paper is intended to introduce a new FastSPICE simulation engine, the XA from Synopsys, and it’s co-sim solution with VCS. Nanosim simulator as a mixed-signal whole chip verification solution has been adopted extensively. Circuit designer found it suitable for large and moderate scale chip verification. But as the circuit’s complexity and the signal speed increase, a new simulation engine which can offer higher speed and acceptable accuracy becomes an emergency. During the multi-channel high speed SERDES chip verification, our team has adopted NIV solution as always. We found it takes about 6 days to simulate a test case. Thinking about the 36 test cases, it will be a nightmare to finish all of the cases. After consulting with the engineer of Synopsys, we are suggested to use a new simulation engine of XA, and the simulation result shows obvious speed advancement.

2. XA-VCS environment

The design flow of HiSilicon analog team use schematic editor and Hspice for analog module pre-simulation and post-simulation. But the transistor-level whole chip verification of a mixed-signal project has been a puzzle for us. For a moderate scale chip verification, we used to us Nanosim-VCS (NIV) to do this. But during our multi-channel 2.5G SERDES full chip co-simulation with all of the analog circuit and digital modules, we found a normal test case will consume about 6 days. It seems our project will have to be delayed and the project deadline will not be satisfied. Our group has to seek help from Synopsys engineer for a better solution, and they recommended the next generation simulation engine of XA to accelerate our co-simulation. The evaluation result shows about 2~30 times speed upgrade relative to our previous solutions (NIV). It is a great speed up for our simulation efficiency. With additional various design types evaluation, we get typically about 10 times speedup than NIV. So the adoption of the newer tools seems to be obvious.

Figure 1.1: XA “Out-of-the-Box” Performance at Prescribed Accuracy

The XA technology is the next-generation transistor-level transient simulator that delivers out-of-box SPICE accuracy while maintaining FastSPICE performance and capacity. XA is designed to augment NanoSim and HSIM to address the need for high accuracy simulation without command option tuning (Figure 1.1). XA provide accelerated simulation of analog and mixed-signal designs even with full layout parasitic. It’s predictable and repeatable SPICE-accurate results improve sign-off confidence. The common HSPICE models and netlist format ensure the ease of adoption. Unlike traditional FastSpice, XA provides intuitive simulation control with a single accuracy setting (set_sim_level) used globally or locally. The XA can also perform co-sim with VCS with the same DKI way of NanoSim to provide outstanding mixed-signal & mixed-language simulation capability as shown below in this paper.

2.1 XA-VCS shell configuration

The XA-VCS simulation environment is easy to setup if you ever used Nanosim-VCS in shell script as figure 2.1，they are almost the same in script configuration. Below figure 2.2 shows the basic introduction of XA-VCS shell configuration. As a contrast some Nanosim-VCS shell scripts listed.

Figure 2.1: Nanosim-VCS shell environment

Figure 2.2: XA-VCS shell environment

Usually we use a GUI interface of Nanosim-VCS to configure our simulation, but if you look up in the simulation directory, you will find the three shell script, tc.run, tc.cfg and tc.ptn (Figure 2.1). Correspondingly, you need three scripts to config the XA-VCS, the runXaVcs, tc_000.cfg and xaVcsMSV.ctrl (Figure 2.2). They are almost the same with Nanosim-VCS, except for some command format. If you are not familiar with these XA scripts, you can use Nanosim-VCS scripts as reference to modify. Figure 2.3 shows the runXAVcs script configuration.

Figure 2.3: runXaVcs shell script

Blow the command is compile stage control of VCS:

VCS \

-f verilog/xxxx_normal.f \

** compile some verlog codes which is include in the xxxx_normal.f

+vcs+dumpvars+./wave/tc_000.vcd \

** save digital wave in ./wave/tc_000.vcd

-Mdir=xaCsrc \

** Main directory of compile file

-o xaVcs \

** object file of compile process

-ad=xaVcsMSV.ctrl \

** Specify the simulation control file.

-l xaVcsLog/xaVcsElab.log

** setup the compile save directory

And then, the next process is the simulation executable run setup.

xaVcs \

** simulate with the object file xaVcs which is created by compile process.

-lca A-2008.03 \

-ucli \

-do xaVcs.ucli \

** setup the interrupt function, during the simulation, you can use CTRL+C and exit to stop it.

-l xaVcsLog/xaVcsRun.log

** setup the simulation log file saving directory.

Figure 2.4 demonstrated the basic control script for the analog part and analog/digital interface description.

Figure 2.4: xaVcsMSV.ctrl control script

spice_top;

** choose analog spice netlist as the simulation nutshell.

choose XA –hspice ./spice/tc_000.sp –o ./wave/tc_000 –wavefmt wdb –c ./tc_000.cfg;

** choose XA as the analog simulator, set hspice as the spice netlist format, save the simulation waveform

with a

name of tc_000.wdb, set the config file name tc_000.cfg.

a2d loth=0.4v hith=0.6v cell=gelinkv100_dig_top port=rstclk;

** set the analog to digital signal threshold.

d2a lov=0v hiv=1v cell=gelinkv100_dig_top port=d2a_rst_n;

** set the digital to analog signal high and low voltage

Figure 2.5 shows the analog part simulation control script, which can contain the hierarchical accuracy and speed trade-off settings even block by block, the output waveform control etc.

Figure 2.5: tc_000.cfg simulation configure script

set_sim_level –level 4

**set simulation accuracy。

Table 1: XA Simulation Level for Different Accuracy

3. Test Cases Description

Our test case include 3 main CMU(clock management module) blocks, Transmitters, Receivers and so on. The top simulation covers all of these analog block and digital verilog modules. Every simulation uses transient analysis to evaluate function. The PLL close-loop simulation uses Nanosim-VCS (via GUI) and XA-VCS to compare the simulation efficiency. The Nanotim and XA simulation level used 3, 4, 5, and 6 respectively. The result of the simulation is listed in the table 2.

3.1 PLL simulation

The TX channel PLL is a crucial block of our CMU，we used Nanosim and XA to evaluate the simulation accuracy & speed . Figure 3.1 shows the element statistics of the TX PLL. Table 2 provided the simulation result with different simulation levels. We can see that the performance can be speed up from 2.3 to about 30 times with various simulation levels. With about the same simulation level, we found that the XA generated results are with more acceptable accuracy. This provides us the much faster turn around time with more accurate solution.

Figure 3.1: XA Element Log of TX Channel PLL

Table 2: The performance comparison with different simulation levels

3.1.1 The simulation result analysis of TX PLL

Figure 3.2 shows simulation result of the PLL. The waveform is displayed and analyzed with Spice Explorer and Waveview. Clkref is the ref of the block, and it comes from an oscillator on the PCB board. Biasn and biasnr is the control voltage of VCO, ref and fbc is the input signal of PFD, UP DN is the output signal of PFD. To evaluate the accuracy and specification of VCO, there are two methods. You can use the simulator’s function or jitter vs time analysis or the eye diagram function of SPICE Explorer.

Figure 3.2: PLL Top Simulation Result

Figure3.3 gives the waves of PLL VCO output with different simulation levels (set_sim_level), the level 3,4,5 and 6. The PLL locks in at about 5us from the waveform and then we can evaluate its performance within the time slot between 5us and 20us, which can be regarded as locked condition.

Figure 3.4: PLL jitter performance: XA Level 3,4,5,6

Figure 3.5 use another method , the eye diagram, to show the jitter with accumulate the transient waveform from 5us to 20us with a time interval of 3.2ns. It can fulfill spec requirement from the eye diagram result.

Figure 3.6: Element statistics of SERDES chip.

The graph of figure 3.8 and figure 3.9 show some crucial clock output waveforms from the PLLs, DLLs, CDRs and PLL VCOs. The jitter vs time plot can give some sense of clock characterization of different clock module.

Figure3.8: SERDES Clock of PLL,DLL,CDR, and VCO

Figure 3.9: Jitter Performance of PLL,DLL,CDR, and VCO

The output performance of Transmitter can be measured with the eye diagram of the serialized signal TXDP. This eye diagram can used to evaluate the output swing and jitter of single serial signal as the waveform of figure 3.10.

Figure 3.10: TXDP and Its Eye Diagram

4. Conclusions and Recommendations

The new generation simulation tools of XA and it’s co-simulation with VCS is introduced to our muti-channels high speed SERDES verification, with the patent-pending technology for array- and rc-optimizing techniques, it accelerate our simulation on with typically about 10 times. Besides this, XA have several advantages we would recommend analog/mixed signal engineers to use:

• Most of XA command is similar with Nanosim, it is easy for a engineer familiarly with Nanosim command to use.

• XA supports all standard industry netlist formats, and offers several waveform output formats such as fsdb,wdb.

• XA can provide SPICE like accuracy, similar capability and much better performance than traditional FastSpice.

The proposal we would like to put table is to offer a GUI interface like Nanosim-gui. It will also be more flexible if the simulation accuracy level could be further expanded.

5. Acknowledgements

We want to appreciate Synopsys Consultant Fansheng Meng for his continues help during our projects development.

6. References

[1] XA Reference Manual , September 2008

[2] XA Command Reference,Version B-2008.09, September 2008.