Abstract

This paper describes we make use of the HSIM and Cosmos Scope flow to design a 1.6Gb/s parallel-link transceiver chip in 0.18um technology . It focuses on our experiences in using HSIM pre-layout and post-layout dynamic simulations to realize a high speed mix-signal design. As a fast spice simulator, HSIM can simulate and analyze the hierarchy and complex circuit accurately. Cosmos scope can view the waveform flexible and fast. The final experiments present that the simulation results of the HSIM and Cosmos Scope are much consistent with those of the equipment measurements.

Key words: HSIM,verilog-A,Cosmos Scope,transeiver

1. Introduction

As is well known, HSIM is synopys’s fast spice simulation tool. It has many features and advantages. A few engineers know that HSIM is very fit for memory design, which can decrease the chip design period much and simulate the design accurately. Meanwhile many chip design experiments show that HSIM can accomplish very complex analog design such as ADC, DAC, and PLL.

We have design a hard IP which realize a high speed multi-channel transceivers in 0.18um CMOS technology. This paper describes the successful simulation of a complete transceiver circuit with HSIM and Cosmos Scope.

The transceiver usually has much complex analog and digital modules. And much simulation and optimization must be needed in the design process. The aim was to verify the functionality and connectivity of a complete RF transceiver chip under actual application conditions. At such a level of complexity, traditional tools do not allow simulation of the design at transistor level in a relative short time. However HSIM can shorten the design period much which has high speed simulation engines. In addition to digital models, mixed-signal behavioural models of the transmitter, receiver and pll have been developed for a high level of abstraction, as required in a top-down methodology. But HSIM is compatible with the new Verilog-A standard. The Verilog-A compiler adds analog behavioral modelling capability to HSIM. The Verilog-A parser reads source code written in the Verilog-A language and provides HSIM with the necessary simulation information. With the Verilog-A feature, designs including Verilog-A modules can be included in the HSIM netlist.The complete simulation of the chip took a few minutes of CPU time for the circuit operation. For the first time we were able to verify and debug such a circuit at the top-level.

Cosmos Scope is a graphical waveform analyzer tool that allows you to view and analyze simulation results in the form of waveforms displayed on graphs.

There are many special features in Cosmos Scope .Firstly , it is a very fast waveform for viewing the graph. If we have a very long time simulation, the waveform file is usually too large however the tool still can open the file quickly the same as opening one small file. Secondly, it has many fast waveform analyzing features which means we can do many various data computing such as FFT, jitter test, eye diagram viewer. Thirdly, Cosmos Scope can read many different file formats; therefore it can be compatible with different simulation tools. In a word, the Cosmos Scope is a expert waveform viewer.

In this paper we present a 0.18um high speed mixed-signal design using Synopsys’ HSIM and Cosmos Scopes. The project proved that HSIM provides the flexibity and efficient simulation with accuracy and speed in 0.18um cmos technology and Cosmos Scope helps to analyze the waveform and estimate the characters of the design. For high-end transactional systems.

Section II and III describes that we utilize HSIM to optimize and analyze the behaviour design by two methods, one is based upon the behavior design and the other is based upon transistor design. Meanwhile we introduce the waveform viewer “Cosmos Scope” which is very helpful to the whole design. Section IV describes the comparable results between simulations and test chip experiments. Section VI concludes the paper.

2. HSIM Behavour Verfication

We have designed a general source 8-bit synchronous transceiver connecting two chips as the high speed bus in figure1. Source synchronous interface is typically split into several clock domains formed by a group of data lines and an associated source synchronous clock. The transmitter sends a parallel word of data along with a clock to the receiver. On the receive side, the data are sampled with the source synchronous clock that always passes through a delay locked loop (DLL). The static skew of the individual data lines is adjusted during link-up using dedicated training sequences for each data pin of the interface.

Fig 1: General Source Synchronous Transceiver

As is shown in figure1, the transceivers are composed of the many custom modules such as the high speed mux and demux, low jitter pll, low noise drivers and receivers. Meanwhile there are a few of analog circuits such as the PLL, and amplifiers. We can see that the whole design is complex and large.

Therefore how to realize the whole architecture and assure the design specification of those circuits is a hard problem. In a conventional design flow, the circuit engineer usually divides such a big macro into several partitions and designs each module independently. However, there are very limited interactions in the flow until full-custom integration and beginning of the simulation and verification of the resulting mixed-signal IP. One more reliable and robust approach is to simulate portions using behavior model first, and then put the results as the reference standards of the transistor level design. This method can decease the design period for mixed signal full custom design espically as the novices. Using HSIM as part of our design flow, we are able to perform fast spice simulation

For simulating the behavior model, we utilize the verilog-A as the descriptions of the hard macro IP. The Verilog-A Hardware Description Language language is a behavioral language for analog systems. The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.

Figure2 shows the design flow of our high speed transceivers. Verilog-A model simulation is the first step in our design. Only if the behavior model is close to the aim of the feature, it will help the engineers to optimize and analyze the transistor level design more easily. By using behavioral modeling technique, and a mixed signal simulation with HSIM, the whole transeiver can be efficiently simulated with good accuracy and reasonable run-time cost. The module characteristic can be parameterized in behavioral representation, and the parameters can be easily extracted from the transistor level simulation. So the first step is utilizing HSIM to simulate the mixed signal behavior model and the pre-layout and post-layout simulation is continued as the second and the third step. Such a whole design process is very compatible with the transceiver design.

Fig 2: General Source Synchronous Transceiver

Otherwise, HSIM has another feature: it has “store” and “restore” installation. The .store statement saves the intermediate simulation data. The .restore statement restores the saved data file. This feature is very helpful to the transceiver design. The reason is that: the transceiver usually can not be steady in a long initial time; if we simulate it each time repeatedly it will waste much hardware resource. And store feature can save the initial time as a “.iic” file so that it do not need to simulate all the time. HSIM option for the “.store” and “.restore” command is displayed as the following figure3.

A. Transmitter Architecture

Figure4 shows a block diagram of the 8-channels transmitter, which has a 8-bit-wide 600Mb/s CMOS-level interface. A 4:1 multiplexer converts 4bit parallel input data into 1 bit wide 2.4Gb/s data, and it only needs two clock cycles.

A designer would thus start the design process by using the behavioral model of the CML transmitter, receiver and PLL focusing on optimizing module parameters. Once enough performance is obtained, the modules can be widely used for various subsystems and in a mixed signal simulations in future designs.

The core output buffer is the CML driver in fig3 and its feature helps to reduce the output jitter. The CML buffer is an absolutely symmetrical architecture. One current source is at the bottom of the driver separately.

For Design Verification purposes, we need to validate that we are connecting inputs to compatible drivers, and that the supplies and biases provided are in the valid range. In addition to checking these, our model needs to provide the correct logic function, output swing, and load on the supply line. When running timing simulation with parasitic capacitance and resistance, we’ll want the model to support analog inputs and outputs. We’ll start with a Verilog-A version of the model, using the architecture shown in Figure5, that meets these needs, and then transform it to an AMS model, which will support event driven simulation for speed in the functional flow, We complete the design by showing the connect modules and connect_rules, that are used in the Verilog-AMS models to support both timing and functional simulation flows.

B. PLL Architecture

Phase-Locked Loop (PLL), which is one of the most important analog-digital mixed-signal circuits in the transceiver, performs her phase synchmnization or frequency synthesis on system LSI. Fig6 shows the architecture of the PLL. The PLL consists of a phase detector, charge pump, a loop filter, a current controlled ring-VCO, and a frequency divider. As shown in Fig.6, this PLL compares the input signal with the output of VCO at the phase detector. Furthermore, the signal corresponding to the phase error passes through the charge pump and the loop filter, and this signal controls the output frequency of VCO. As the result of this feedback process, the output frequency of PLL is synchronized with the input one. In this architecture, the digital circuit part is the phase detector, and the analog circuit parts are the charge pump, the loop filter, and VCO. It is considered that the variation of the power supply voltage affects to the charge pump and VCO in the analog circuit parts particularly. The following sections show the effects on the charge pump and VCO and the behavior descriptions with Verilog-A.

Fig 6: PLL Architecture

Fig 7: pll divider verilog-a description

A well-known sequential-logic PFD shown in Figure8 is used for phase/frequency detection circuit. This PFD produces UP and DOWN signals depending on the phase difference between reference clock and feedback clock.The behavioral model of PFD can be represented as shown in List.1. This module monitors the phase difference between the clocks. When the rising edge of REF clock occurs before the rising edge of FB clock, the module activate UP signal and then forces the VCO to increase the oscillation frequency. In the reverse case, the module activate DOWN signal and forces the VCO to decrease the frequency. Note that UP and DOWN signal are active-low and active-high respectively.

Fig 8: pll pfd verilog-a description

C. Cosmos Scope viewing simulation results

We utilize Cosmos Scope to view the behavior simulation and transistors simulations. Figure9 and figure10 display the pfd and the vco output results. From the simulation results, we can conclude that HSIM and Cosmos Scope can realize the behavior simulation easily and we do not need to change other tools and simulate the transistor circuit with the same tools.

Fig 9: coscope pfd output waveform

Fig 10: coscope vco output waveform

An eye diagram is used to display the behavior of a waveform cycle during a specific period of time. The eye diagram Measurement dialog has the ability to effectively overlap periods of time within a specified periodic waveform.

3. HSIM Transistor Verfication

HSIM is a fast spice tool for simulating millions of transistors. In our design, there are more than fifty thousand transistors in pre-layout circuit. And there are more than five million transistors in the post-layout circuit. To the pre layout simulation HSIM can only accomplish the period in thirty minutes at “ HSIMspeed=1” that is relatively not very accurate. Although to the post-layout simulation HSIM can finish the whole simulation for about twenty hours at “HSIMspeed=1” that is relative fastest tool to realize the simulation including so many parasitic circuits.

HSIM is compatible to the hspice. Therefore we can utilize it to do some monte carlo simulations. The following is the HSIM monte calro options for 2000 times simulation. That flow will take a long time but it is necessary for the mixed signal design.

Fig 12: HSIM monte carlo option

4. Simulation Rusults Comparsion

A test chip of the 8-channel source synchronous macro cell with ESD circuit was designed and fabricated in the ST micro 0.18um process technology. The figure5 shows that the 8bit transmitters and receivers with one middle clock channel are on the opposite side of the chip, which is profit to transfer the signal from one chip to another chip during the chip measurement. The fig13 is the die photo. The entire transceiver chip area is 2mm x 2mm. The test chip is packaged with 40-pins QFP.

Fig 13: Die photograph of the transceiver

Fig.14 shows the measured data and clock transmitter signals for the 30cm differential FR4 microstrip lines. We designed a 231-1 PRBS pattern in the transmitter and measured the jitter at the end of the receiver test chip. The eyedigram of two channels( one is data transmitter and the other is clock transmitter) is tested by the Agilent 86100c.The waveform shows that the oscilloscope’s output diagram is consistent with the Cosmos Scope’s waveform.

Fig 14: Die photograph of the transceiver

5. Conclusions

In this paper, we use Synopsys tool HSIM and Cosmos Scope to realize a large and mixed signal design. Its design flow is very helpful to the engineers because we do not need to change design tools in the whole flow and it is easily to be controlled. The experiments results show that the simulation tools can accomplish the design in a relatively accurately and fast manner in 0.18um technology.

6. References

[1] HSIM reference guide

[2] HSIM user guide.

[3] Cosmos Scope manual.

[4] Verilog-A user manual