Abstract

During the low power designs development at Actions, we evaluated Synopsys Liberty NCX for low power cells characterization and library re-characterization at specific PVT corners. This paper mainly introduces how to use Liberty NCX tool to do liberty characterization of various low power cells. Low power design is very popular in modern consume SOCs. In these designs you have to adopt some special cells such as level-shift, always-on, clock gating, retention cell, etc. However, designers have to design, layout and characterize these special cells by themselves if the IP vendors can not provide them. In our design, there are level-shift, always-on, clock gating cell and so on. When we finished the design and layout of the low power cells, we performed the liberty characterization with Synopsys Liberty NCX with power and ground information at specific PVT corners. The paper also described some more Liberty NCX usage, such as re-characterization, library Quality Assurance and so on. The created low power cells and re-characterized libraries are containing pg_pin, voltage_map and related attributes, which are essential for UPF low power flow usage. With Liberty NCX generated libraries as evaluated, the low power designs can be fluently implemented to guarantee tape out success.

Key Words: Liberty NCX, HSPICE, CCS, Level shift, Always-on, Clock gating, Low power, UPF

 

1. Introduction

Today the advanced low power methodologies such as multivoltage require various new librarycells that need additional modeling attributes. These additional new low power cells are very essential for these advanced designs. At the voltage interface in a multivoltage design, the signal connects to logic at different voltage levels. To transmit the signals correctly, level shifter cells are used for all the nets at the voltage interface. If your design contains shut-down area, isolation always on and retention cells may have to be required. Clock gating technique has been broadly used for as an effective technique to reduce dynamic power, In order to reduce dynamic power consumption, you may also need clock gating cell. In order to drive the implement tools during the library selection, you have to provide the liberty of the additional low power cells.

Generally, design and layout these low power cells are about the same with standard cells. But, how to characterize them with suitable liberty format? How to use them correctly in your low power design flow? What should you do specially on these cells? This paper shares experience of the characterization of low power cells with Liberty NCX.

Figure 1.1: About Liberty NCX

Liberty NCX is a powerful standard cell library characterization tool as Synopsys announced. Liberty NCX reads transistor level information for each cell in a library and, using SPICE simulation, generates timing, signal-integrity and power models in the Liberty (.lib) format. Liberty NCX was architected from the ground up around high accuracy Composite Current Source (CCS) models as figure 1.1 shows. It will generate the most accurate and efficient CCS and Variation Aware models in the industry. Liberty NCX is more tightly linked with HSPICE so it runs very efficiently for optimal utilization of resources. The tool also comes with a utility to generate CCS noise data, make_ccs_noise. Liberty NCX includes Library Compiler which has been enhanced to perform quality assurance on the library data to ensure high accuracy. Liberty NCX handles a wide range of cell types, including standard cells, I/O cells, low power cells and other complex cells. Here below we will showcase Liberty NCX for low power cells characterization on the level shift, always on and clock gating cells as demonstration.

The Liberty-NCX tool can generate multi-format timing and power libraries such as NLDM , NLPM, CCS ,ECSM, etc. It supports various simulators, including HSPICE, Eldo and Spectre. We adopted HSPICE as accurate characterization simulator.

2. Level Shift and Always on cell

2.1 Level Shifter

To transit the signals correctly, level shifter cells (also known as buffer-type level shifters) are used for all the nets at the voltage interface. To speed automation of a Synopsys multivoltage design flow, complete information about level-shifter characteristics is required. Implementation tools need the following information from the cell library:

• Which power and ground pin of the level shifter is used for voltage boundary hookup during level shifter insertion. This information allows the optimization tools to determine on which side of the voltage boundary a particular level shifter is allowed.

• Which voltage conversions the particular level shifter can handle. Specifically, does the level shifter work for conversion from high voltage to low voltage (HL), from low voltage to high voltage (LH), or both?

• The input and output voltage ranges for a level shifter under all operating conditions.

2.1.1 Level Shift Cell Model

Figure 2.1 shows a simple low-to-high (LH) level-shifter cell model. You can see there are two power supplies (VDD1, VDD2) and 1 ground (VSS).

Figure 2.1: The LH Level Sheft Cell Model

2.1.2 Circuit schematic

Figure 2.2 shows an actual circuit schematic of LH level-shifter cell with inverter as buffers.

Figure 2.2: LH Level Shift Schematic

2.1.3 Level Shift Layout

Figure 2.3 shows an actual layout of LH level-shifter cell. There are two power supplies. The height of this cell is three times of common standard cells.

Figure 2.3: Level Shift Layout Example

2.1.4 Parasitic extraction

After the layout and physical verification, parasitic extraction should be performed for postlayout simulation to get the most accurate parameters.

2.1.5 Liberty characterization using Synopsys NCX

Liberty-NCX basically provides two library characterization flows, creation and re-characterization. The library creation flow uses a library template, Library index file and cell level templates to generate a new library. The templates can be created from scratch or generated by Liberty-NCX from a similar seed library. The user would have to modify the templates as required to get the desired library. Liberty-NCX also supports a recharacterization flow. The recharacterization flow reads in an existing seed library and recharacterizes the timing tables, power tables, design rules (max-capacitance,max-transition), pin capacitances, and setup/hold constraints as instructed by the user with specific PVT corners. Here we will just discuss the first flow.

Liberty NCX uses a configuration to define the required information for characterization and customize the generated library meet user needs. During execution, a logfile is created detailing progress during characterization and library generation.

Before characterization, some files as below should be prepared:

• Cell spice netlist (with post-layout parasitic parameter)

• Transistor process/SPICE model file (from the foundry)

• Cell description or a similar library file (seed library, optional).

Liberty NCX runs a circuit simulator under the hood using distributed processing or on a single cpu. It will need two configure files with 2 characterization steps.

File below (configfile1) is an example used for generating the library template from a seed library.

set input_library ./import_lib/levelshift_ff.lib ## imput seed liberty file name

set work_dir mywork

set output_library ./out_libs/levelshift_ff_ccs.lib ## output liberty file name

set log_file ./log/ncx.log

set templates true

set output_template_dir templates ## output temlate directory

File below (configfile2) is an example used for simulation and characterization.

set model_file ./spicemodel/modelfile.sp

set netlist_dir ./netlist

set netlist_suffix .spi ## define spice file suffix,default is .spc

set work_dir mywork

set output_library ./out_libs/levelshift_ff_ccs.lib

set log_file ./log/ncx.log

set input_template_dir templates

set simulator_exec /install_path/HSPICE/Y-2008.09/bin/hspice ##simulator

set simulation_dir ./ sim_data

set timing true ##acquire NDLM/CCS timing models

set power true ##acquire NDLM/CCS power models

set ccs_timing true ##acquire CCS format timing models, default is true ,if you do not want CCS format, you can change it to false

set farm_type nofarm

#set farm_type LSF ##or Sun Grid

#set queue_name normal

#set max_jobs 10

The lines in bold print are used to define whether the SPICE simulations are run on an LSF/Sun_Grid batch queuing system or not. If you want to run on LSF, you would delete the “#” characters and edit the queue name and number of jobs to reflect the queuing configuration desired.

To execute commands in the configfile1 :

>ncx –f configfile1

In the templates directory you will find 3 types of template related files after executing the 1st script. They are the library template file, cell template files and library index file. In the library template file you can modify the name and value of voltage supplies accordingly. You can define input slews and output loads if different with the seed library. Below is a generated Library template file example:

……

ncx_use_pg_pins : true ## if you choose false, the output liberty file will not contain pg_pin infomation

power_supply {

default_power_rail : VCC;

power_rail : VCC 1.32000000;

power_rail : VDDI 1.10000000;

power_rail : VSS 0.00000000;

}

operating_conditions typ {

process : 1.0000000 ;

temperature : 0.0000000 ;

voltage : 1.32000000 ;

tree_type : balanced_tree ;

power_rail : VCC 1.320000000 ;

power_rail : VDDI 1.100000000 ;

power_rail : VSS 0.000000000;

}

……

Include levelshift_ff_ccs.indexes ;

……

The levelshift_ff_ccs.indexes defined the input slews and output loads. The index data will follow the input library file. You can change them to your convenient values to control the new library.

A library indexes example:

* Generated by Liberty NCX vB-2008.06

ncx_input_transition_time_index : 0.0196 0.0294 0.049 \

0.0882 0.1664 0.323 0.6362 ;

ncx_input_net_transition_index : 0.0196 0.0294 0.049 \

0.0882 0.1664 0.323 0.6362 ;

ncx_total_output_net_capacitance_index : 0.0005825 0.002097 0.005126 \

0.0110675 0.023067 0.047066 0.095064 ;

ncx_total_output_net_capacitance_index_1 : 0.00233 0.008388 0.020504 \

0.04427 0.092268 0.188264 0.380256 ;

In cell level templates you can modify characterization parameters such as which slope or load index to choose for an individual arc. The pin name and In/Out property in the cell template file must be consistent with cell’s SPICE netlist. Below shows an example of an in house level shift cell template file:

* Generated by Liberty NCX vB-2008.06

cell_footprint : lvlu ;

rail_connection : VDDI VDDI ;

rail_connection : VCC VCC ;

area : 43.6800000 ;

is_level_shifter : true ;

define valid_location : to ;

cell_leakage_power : 973.4490000 ;

ncx_leakage_power_when : !A !A A A ;

pin A {

direction : input ;

input_signal_level : VDDI ;

}

pin Y {

direction : output ;

output_signal_level : VCC ;

function : A ;

max_capacitance : 0.0950640 ;

ncx_internal_power_rise_input_transition_time_index : 0 ;

ncx_internal_power_fall_input_transition_time_index : 0 ;

ncx_internal_power_rise_total_output_net_capacitance_index : 0 ;

ncx_internal_power_fall_total_output_net_capacitance_index : 0 ;

ncx_rise_input_net_transition_index : 0 ;

ncx_fall_input_net_transition_index : 0 ;

ncx_rise_total_output_net_capacitance_index : 0 ;

ncx_fall_total_output_net_capacitance_index : 0 ;

}

pg_pin VCC {

voltage_name : VCC ;

pg_type : primary_power ;

}

pg_pin VDDI {

voltage_name : VDDI ;

pg_type : backup_power ;

}

pg_pin VSS {

voltage_name : VSS ;

pg_type : primary_ground ;

}

The is_level_shifter simple attribute has been added at the cell level to identify a library cell as a level shifter cell. If it’s an enable level shifter, the level_shifter_enable_pin boolean attribute at the pin level is available to help client tools to identify the enable input pin of a level-shifter cell.

When you finished modifying the template file, you can execute the final step to perform characterization. Liberty NCX will automatically call HSPICE for various arcs simulation and generate the library files.

>ncx –f configfile2

After the Liberty NCX tool finishes, view the ncx.log file in the editor of your choice. You should see that defined cells were acquired sequentially. The input slews and output loads used during acquisition are defined in the cell templates. If there are any failures, they will be detailed at the end of the log file. You simply need to search for the word, “Failed”. If the word does not exist, then all acquisitions for all cells completed. Then, you can find the result in output_library directory you defined in configfile2.

For example:

……

cell (LEVELSHIFT) {

cell_footprint : “lvlu”;

area : 43.680000;

is_level_shifter : true;

pg_pin VCC {

voltage_name : VCC ;

pg_type : primary_power ;

}

pg_pin VDDI {

voltage_name : VDDI ;

pg_type : backup_power ;

}

pg_pin VSS {

voltage_name : VSS ;

pg_type : primary_ground ;

}

valid_location : “to”;

cell_leakage_power : 9.734490e+02;

driver_waveform_rise : “preDrv”;

driver_waveform_fall : “preDrv”;

rail_connection(”VCC”, \

“VCC”);

rail_connection(”VDDI”, \

“VDDI”);

rail_connection(”VSS”, \

“VSS”);

pin (A) {

direction : “input”;

input_signal_level : “VDDI”;

fall_capacitance : 0.001678;

fall_capacitance_range(0.001582,0.001796);

capacitance : 0.001852;

rise_capacitance : 0.002026;

rise_capacitance_range(0.001622,0.002413);

}

pin (Y) {

direction : “output”;

output_signal_level : “VCC”;

function : “A”;

max_capacitance : 0.095064;

timing () {

related_pin : “A”;

timing_type : “combinational”;

timing_sense : “positive_unate”;

cell_rise (”del_1_7_7″) {

index_1(”0.0196, 0.0294, 0.049, 0.0882, 0.1664, 0.323, 0.6362″);

index_2(”0.0005825, 0.002097, 0.005126, 0.0110675, 0.023067, 0.047066, 0.095064″);

values(”0.1421091, 0.1485794, 0.1598593, 0.1807104, 0.2222225, 0.3051530, 0.4712082″, \

“0.1449947, 0.1515229, 0.1627769, 0.1835622, 0.2252369, 0.3081472, 0.4740863″, \

……

You can find that the header and index are following what you defined in templates.

2.2 Always-on cell

Always-on (AO) cells remain powered on even when the main power supply is switched off. These cells have a secondary power pin that supplies current when the main supply is switched off. Always-on cells can be used during always-on synthesis to optimize always-on nets. Always-on pins are input pins that maintain a valid signal even when the main power is shut down. Galaxy client tools are able to use always-on pins to trace connectivity backward and determine, based on the power domain, which nets are always-on nets.

2.2.1 AO Cell model

Figure 2.4 shows the always-on buffer cell model. The blue arrows in the schematic highlight the signal pins that are associated with the power and ground (PG) pin pairs.

Figure 2.4: Always-On Cell Model

2.2.2 AO Cell Schematic and Layout

The circuit of always-on buffer cell is the same as common buffer cells. Figure 2.5 shows the layout of an always-on cell. It has 2 power supplies VCC and VDDG. The height of always-on cell is two times of common standard cells.

Figure 2.5: AO Layout Example

2.2.3 AO Cell Liberty Characterization

Fellow the same flow of level shift characterization, you can get the AO cells liberty file. For example :

……

cell (ALWAYSONBUF) {

cell_footprint : “gpgbuf”;

area : 4.480000;

dont_touch : true;

is_always_on : “true”;

pg_pin VCC {

voltage_name : VCC ;

pg_type : primary_power ;

}

pg_pin VDDG {

voltage_name : VDDG ;

pg_type : backup_power ;

}

pg_pin VSS {

voltage_name : VSS ;

pg_type : primary_ground ;

dont_use : true;

cell_leakage_power : 8.832222e+01;

driver_waveform_rise : “preDrv”;

driver_waveform_fall : “preDrv”;

rail_connection(”VCC”, \

“VCC”);

rail_connection(”VDDG”, \

“VDDG”);

rail_connection(”VSS”, \

“VSS”);

pin (A) {

direction : “input”;

input_signal_level : “VDDG”;

rise_capacitance : 0.001440;

rise_capacitance_range(0.001325,0.001646);

capacitance : 0.001399;

fall_capacitance : 0.001359;

fall_capacitance_range(0.001301,0.001480);

}

pin (Y) {

direction : “output”;

output_signal_level : “VDDG”;

function : “A”;

max_capacitance : 0.095064;

timing () {

related_pin : “A”;

timing_type : “combinational”;

timing_sense : “positive_unate”;

cell_rise (”del_1_7_7″) {

index_1(”0.0196, 0.0254, 0.037, 0.06, 0.1062, 0.1988, 0.3836″);

index_2(”0.0005825, 0.002097, 0.005126, 0.0110675, 0.023067, 0.047066, 0.095064″);

values(”0.0328035, 0.0374669, 0.0457582, 0.0610532, 0.0916542, 0.1521879, 0.2732713″, \

“0.0342888, 0.0389450, 0.0471887, 0.0625096, 0.0930169, 0.1538481, 0.2755237″, \

……

The pin with always_on attribute in an always-on cell must be related to a backup power supply type of power and ground (PG) pin.

3. Clock Gating Cell

Figure 2.6 shows a representative clock gating cell.

Figure 3.1: Clock Gating Cell Model

Yon can see that the cell contains two standard cells, one is flip flop and the other is and2. You can use both the transistor level and gate level netlists for liberty characterization. Transistor level netlist is preferred and more precise.

Here is an example of a clock gating cell in house, which characterized by Synopsys liberty NCX

cell (CLOCKGATING) {

area : 66.528000;

dont_use : true;

dont_touch : true;

clock_gating_integrated_cell : “latch_posedge_precontrol”;

driver_waveform_rise : “preDrv”;

driver_waveform_fall : “preDrv”;

statetable (”CLK EN TE”,ENL) {

table : “L L L : – : L,\

L L H : – : H,\

L H L : – : H,\

L H H : – : H,\

H – - : – : N”;

}

pin (CLK) {

direction : “input”;

max_transition : 1.050000;

clock_gate_clock_pin : true;

original_pin : “CLK”;

rise_capacitance : 0.004342;

rise_capacitance_range(0.003630,0.004745);

capacitance : 0.004137;

fall_capacitance : 0.003931;

fall_capacitance_range(0.003533,0.004402);

timing () {

related_pin : “CLK”;

timing_type : “min_pulse_width”;

related_output_pin : “ENCLK”;

fall_constraint (”constraint_6_0_1″) {

index_1(”0.0200000, 0.0800000, 0.1700000, 0.3600000, 0.6000000, 1.0500000″);

values(”2.3634332, 2.4443330, 2.4469688, 2.4522402, 2.4575117, 2.4627833″);

}

}

}

pin (ENL) {

direction : “internal”;

internal_node : “ENL”;

}

pin (EN) {

direction : “input”;

max_transition : 1.600000;

clock_gate_enable_pin : true;

original_pin : “EN”;

rise_capacitance : 0.002262;

rise_capacitance_range(0.001947,0.002502);

capacitance : 0.002159;

fall_capacitance : 0.002056;

fall_capacitance_range(0.001843,0.002243);

timing () {

related_pin : “CLK”;

timing_type : “setup_rising”;

rise_constraint (”vio_6_6_1″) {

index_1(”0.0200000, 0.0800000, 0.1700000, 0.3600000, 0.6000000, 1.0500000″);

index_2(”0.0200000, 0.0800000, 0.1700000, 0.3600000, 0.6000000, 1.6000000″);

values(”0.1220794, 0.1393373, 0.1528813, 0.1762416, 0.1881250, 0.1996786″, \

From the example we can see obviously liberty NCX can support all of the state tables of clock gating cell. You might notice that the index in the example just contains 6 not 7 input data. Initially there were 7 input data when we finished creating library template index begin with ‘0’. It’s not allowed for Liberty NCX with “0” transition. It has to be change to a nonzero data in the version we evaluated then. As following up, Liberty NCX can automatically control this situation in the present versions.

4. Library Quality Assurance

The library Quality Assurance (QA) system provides syntax checking, screening, validation and correlation capabilities (Figure 1.1). Library QA supports Timing, Noise and Power. Library Compiler can validate the contents of the library to ensure the model data is consistent and reasonable. You will use Library Compiler to ensure that the library you created is a good library. Validation execution is controlled through the use of a configuration file. Library Compiler will check for consistency between NLDM and CCS data and ensure the CCS timing model is reasonable. The output of validation can be in both HTML and comma-seperated-value (CSV) formats. Library QA Correlation meant to run on a subset of library cells to determine confidence of overall library with golden accuracy tools PrimeTime and HSPICE. CCS timing correlation is run on a test circuit as shown in figure 4.1, where cell1 is the driver cell. The correlation will performs PrimeTime analysis of the test circuit using different combinations of slew and output load. HSPICE simulations performed on the test circuit under the same sets of conditions. The QA system will compare PrimeTime calculated delay and slew time values against HSPICE results. The correlation results are available in HTML and .csv format. The .csv files can be imported into any spreadsheet program.

Configuration file for CCS timing correlation may contain following commands:

• Input library file, Cell List

• Path to PrimeTime, HSPICE

• Location of the SPICE sub-circuits

• Type of correlation

CCS timing correlation run command file example:

set library_file lib_file_path

set db_file db_file_path

set pt_shell_path pt_shell_path

set simulator SPICE_simulator_path

set spice_header_path SPICE_common_header_path

set netlist_path SPICE_cell_netlist_directory

set vdd_name VDD_name

set vss_name VSS_name

set spice_file_suffix net | sp | typ | …

set correlation_arcs min | most | all

set waveform predriver | pwl | real | user

set correlation_type ccs_timing | nldm_timing

set lsf_correlation yes| no

set cells {cell_list}

run correlation

5. Conclusions and Recommendations

Liberty-NCX provides a very easy and fast way to characterize full custom design cells and I/O cell compare with our current characterization methodology. It can support NDLM, CCS , ECSM library format. Especially under 65um process, CCS library is indispensable for RTL synthesize and physical implementation. The re-characterized and created low power cells libraries are containing pg_pin, voltage_map, related_power_pin and related attributes, which are essential for UPF low power flow usage. With the generated low power cells liberty, we can implement our low power flows fluently with accuracy confidence. The characterized low power cells and the recharacterized specific PVT corner libraries can be successfully adopted to our low power designs and ensure the successful tape-out.

6. Expectation and Acknowledgements

In addition to characterize the low power cells, Liberty NCX supports various functionalities which attract interests such as variation aware (mismatch) characterization, CCS noise, Verilog and datasheet generation, efficient multi-core and so on. We would like to try more in the future. We also would like to take this opportunity to appreciate the support of Actions management and professional technical support from Synopsys.

7. References

[1] Synopsys “Liberty Syntax for Level-Shifter and Isolation Cell Modeling Application Note Version 1.0 A-2007.12, December 2007”

[2] Synopsys “Liberty Syntax for Always-on Cells Application Note Version 1.0 A-2007.12, December 2007”

[3] Synopsys “Module Characterize Complex Cell”

[4] Synopsys Liberty NCX User Guide Version B-2008.06, June 2008

[5] ARM “Product Application Note Power Management Kit 1.1 July 2007, Document Revision 1.2”

[6] Michael Keating, etc. Low Power Methodology Manual for System-on-Chip Design. Springer, 2008

8. Appendix

Tools adopted:

• Liberty NCX B-2008.06

• Hspice B-2008.09

• StarRCXT

• SpiceExplorer A-2008.03