Abstract

As power has become one of the key concerns of chip design, many new power management techniques, like Power-gating, Multi-Voltage, etc., has been introduced. These techniques bring many verification challenges as well as design challenges.

The objective of this paper is to share our experiences of verifying a multimedia SoC with Synopsys’ low-power verification suite, MVSIM and MVRC. In simulation-based verification, MVSIM was used together with VCS, to help the logic simulator correctly understand the voltage information; in static verification, MVRC was used to check the architecture and structure of the chip. The low power verification was successfully accomplished in a short time, without major changing on the existing verification flow.

Key words: SoC, Low Power, Verification, Power Gating, Multi-Voltage

摘要

随着功耗成为芯片设计中的一个重要考虑因素，多种新技术，如电源关断（Power Gating）, 多电压（Multi-Voltage）等，被越来越多的项目所采纳。然而由此带来的全新的验证挑战却无法由传统的验证方案所解决。

本文介绍了VIMICRO采用Synopsys 新的低功耗验证工具，MVSIM和MVRC，对一个使用了先进低功耗设计技术的多媒体SoC进行验证的成功经验。在基于仿真的验证中，使用了MVSIM与VCS配合，使得逻辑仿真器VCS能够理解电压的动态信息；在静态验证中，使用了MVRC对芯片进行架构及结构的验证。在基本保留原工作流程的基础上，用很短的时间完成了低功耗的验证工作，并取得了良好的效果。

关键词：SoC，低功耗，验证，电源关断，多电压

1. Introduction

Power management is one of the key concerns, if not the key concern, of modern SoC designs. With battery technology not keeping the pace with semiconductor technology node, minimizing the power consumption, especially in portable devices, is becoming a greater challenge.

Traditionally, chip designers use Clock-Gating (Use clock gating cells) and/or Multi-Vth (Use multi threshold libraries) to reduce the power consumption. Given the fact that the major power consumption is from static power (in deep submicron design (=<90nm) the static power is comparable or even greater (for lower technology nodes =< 65nm) than dynamic power), these traditional techniques are not sufficient for modern designs. There are several advanced power management techniques that are emerging from the horizon. These techniques include: Multi-Voltage, Power-Gating, Retention, Dynamic/Adaptive Voltage Frequency Scaling, which are shown in Figure 1.

Figure 1: Advanced power management techniques

1.1 New bugs introduced by power management

Although these new low power design techniques greatly help to reduce the power consumption, they also introduce some critical bugs which cannot be handled by traditional EDA tools. These new bugs include: isolation/level shifting bugs, control sequencing bugs, power sequencing errors, power gating failure, power on reset problems, retention bugs, etc. That means the verification must be aware of power states, transitions and sequences, and must be aware of the waveform nature of supply voltage.

1.2 New requirements for EDA tools

Traditional EDA tools are able to co-work with each other on the design logics. However, when it comes to power supply, it is not the case. Traditional EDA tools are either cannot understand power information or cannot export/import the power information to/from other tools. Since there are different verification needs at different verification phases, SoC designers have to develop their own methods to define the power information for all the tools throughout the whole design and verification flow. These home-build methods increase the complexity of design and verification work, as well as increase the communication iterations between different teams.

Therefore, effective low power design requires the co-work among SoC designers, EDA vendors, IP vendors.

Synopsys, the leading EDA and IP vendor, has always been focusing on low power design and verification techniques. Synopsys co-published “Low Power Methodology Manual” with ARM. Synopsys also co-published “Verification Methodology Manual for Low Power” with ARM and Renesas. Besides the public methodologies, Synopsys also offers the market s total solution for low power design and verification, which supports UPF, the IEEE P1801 standards, as well as being compliant with LPMM and VMM-LP. With this total low power solution, Synopsys is able to help SoC project teams to address the design and verification challenges in an already tight schedule.

2. Verification flow for low power designs

In the design and verification teams at VIMICRO, a concerted effort was made to develop a power management verification flow, which could be run at RTL level as well as at gate level. This was necessary because VIMICRO designs were moving towards adopting aggressive power management techniques and developing the ability to verify these features upfront in the design cycle was of significant importance. The design and verification teams identified two core abilities that had to be present in a verification methodology for low power designs. They were:

(1) The ability to simulate power up/power down activity for the power islands and having X’s or Z’s propagates in simulation when the islands are down.

(2) Ensure that isolation devices and level shifters are correctly placed for signals crossing over from one power island to another.

2.1 MVSIM/MVRC tool suit overview

The MVSIM/MVRC tool suit was chosen because it enables verification of power managed designs at the RTL level as well as at the gate level, as shown in Figure 2.

MVSIM is a multi-voltage simulation tool that enables multi-voltage simulation and verification. MVSIM works in conjunction with industry-standard simulators such as VCS, NC-Verilog, and ModelSim, to verify the impact of voltage changes in a power managed chip.

MVRC works in a static fashion, which means that MVRC does not need a testbench and test vectors, to verify the correctness of the different multi voltage objects in the design. This allows the designers to comprehend the correctness of their design with respect to the multiple voltages used across several blocks at a very early stage in the design flow as well as at the gate level.

Figure 2: MVSIM/MVRC tool suit

2.1.1 Power awareness in simulations

The usual simulation assumes that the logic is always powered and most of the simulation carries out with values being changed to high or low and tri-state if required. As the RTL code normally does not have the power pins, retention control etc, with traditional simulators one cannot verify the different power states, like Island Sleep/Shutdown Modes. So there is a need to add power awareness to these simulators. MVSIM is such kind of tool, which makes traditional logic simulators power aware.

MVSIM enables verification of power managed designs at the RTL and gate level. It provides a comprehensive verification solution to the multi-voltage design. MVSIM annotates the multi-voltage information with the RTL and works with existing functional simulators to perform a multi-voltage verification. This allows a design team to comprehend the correctness of their design with respect to the multiple voltages used across several blocks at a very early stage in the design flow. MVSIMTM can accurately simulate techniques such as, Multi-Voltage, Power-Gating, Retention, and Dynamic/Adaptive Voltage Frequency Scaling. Below are the main features of MSIM.

• Voltage-Aware simulator – Provides electrical accuracy

• Works both at RTL and Gate level – Enables verification at early phase

• Built-in automated assertions for all LP design techniques – Improves verification productivity and ease of debug

• Automated coverage of power FSM – Measure of LP verification progress

With MVSIM, one can describe how a chip/block is powered on/off by defining a voltage ramp function. Figure 3 shows an example code snippet and the waveform.

Figure 3: Accurate voltage modeling

Figure 4 illustrates the power gating verification ability of MVSIM. With the presence of MVSIM, traditional logic simulators are able to understand the power control signal and the current power state. In the simulation waveform, as the “sleep” signal goes active, the supply power is cut off. So the outputs go to high Z’s and propagate X in the following block. After the block is powered on, the registers need to be re-initialized. Besides making the logic simulator power aware, MVSIM also generates automatic assertions, which can be used to monitor power on/off sequence.

Figure 4: Verifying power gating

2.1.2 Static verification using MVRC

Identifying the issues associated with low power design techniques early in the design cycle is important for achieving high productivity in the design process. This early stage low power rule verification step not only ensures more optimized designs but also helps in achieving an improved efficiency for the rest of the design flow.

MVRC enables vector less detection of any connectivity and power sequencing errors in the design. It detects any missing, illegal, or redundant protection gates, and also performs various static architectural checks on the design.

Apart from these static rule checks, MVRC provides an interactive interface to query the multi-voltage database. One can use MVRC to obtain specific information about the entire design, or a signal connected between two domains. Below are the main features of MVRC.

• Rich set of Architectural checks – Finds bugs at RTL without simulation cycles

• Works both at RTL and Gate level – Enables verification at early phase

• Comprehensive set of Structural and PG checks – Verifies insertion and connection of power management hardware

• Power up and down sequence validation and prediction – Power cycles thoroughly validated without testbenches

• Hierarchical power state analysis – Reduces verification effort for designs with large number of power domains

2.2 Low power verification flow using MVSIM and MVRC

HDL designs can be statically and dynamically verified using MVSIM and MVRC respectively. The following is the verification flow using MVSIM and MVRC, which is also illustrated in Figure 5.

Figure 5: power verification flow using MVSIM and MVRC

(1) Use the Multi-Voltage Compiler (MVCMP) to compile the design along with power intent files, and the testbench, which is used by MVSIM. The power intent is specified using UPF. MVCMP compiles these files into a binary design view. It also checks for syntax and semantic errors in your design files.

(2) Use the Multi-Voltage Database Generator (MVDBGEN), to elaborate the design and generate the Multi-Voltage Database (MVDB). MVDBGEN reads the binary design view created by MVCMP to generate this database. MVDB contains details about all the multi-voltage objects and partitions in your design.

(3) Use MVRC to validate the power management architecture of the design without a testbench and test vectors. MVRC performs various structural and architectural checks on the design.

(4) Use MVSIM to dynamically verify the multi-voltage behavior of the design. MVSIM works in conjunction with VCS and other industry-standard simulators.

3. VC08XX SoC

VC08XX is designed for mid-tier multimedia feature phones. It is a next generation mobile multimedia processor with outstanding multimedia processing features such as multi-standard video, multi-standard audio, high quality still-image preview, etc. It also contains rich and flexible interfaces. Figure 6 illustrates the chip blocks of VC08XX.

VC08XX integrates multiple codec and decoders and built-in LCD controller. The embedded ARM processor inside VC08XX makes it possible to run various RTOS.

Figure 6: Chip block diagram of VC08XX

Along with the powerful processing ability, the power consumption has also raised to such a level that advanced power management technique, such as Power-Gating, has to be applied to this complex SoC. It is decided to group function blocks into several power islands, and to have separate power supply for each island. According to the current operation mode that the SoC is operating, one or more islands can be switched off. To illustrate the idea without too much baffling design details, a conceptual map of power islands in VC08XX Core is shown in Figure 7.

Figure 7: Power islands of VC08XX Core

Although theoretically there could be 23=8 power states in VC08XX Core, only three of them are defined to be legal, which are shown in Table 1

Table 1 Legal Power States in VC08XX Core.

ls.rails = {Vdd, VDD_CORE_A, VDD_CORE_B, VDD_CORE_C};

ls.state[“Some_OFF"] = {on, off, on, on};

ls.state[“More_OFF“] = {on, off, on, off};

ls.state["ALL_ON"] = {on, on, on, on};

4. MVSIM and MVRC on VC08XX

VIMICRO chose MVSIM and MVRC to perform the low power verification on VC08XX. The results obtained after running are discussed in the following sub sections. The results for the static checking are followed by the results of the dynamic verification.

4.1 Static checking using MVRC

First, describe the power intent for MVTools. The power intent file contains the information of power islands, power supply nets, power ports of islands, indicator signals for power switches, legal power states, and legal power transitions. Then, MVCMP was used to compile the design along with power intent file. After the compilation is done, MVDBGEN generated the database which is ready for use. At the last, MVRC performed the wanted static rule checking on the elaborated database and generated the reports. Following is a summary of the checks that were performed on VC08XX and the reports.

4.1.1 Multi-Voltage database building and power intent syntax/semantic checks

MVCMP and MVDBGEN are used to generate the Multi-Voltage database. MVRC checks for syntax and semantics errors. The commands used are as below.

% mvcmp –mv overlay.h // compile the power intent file

%mvcmp design.v // compile the design files

%mvdbgen –top vc08xx-L ./db/vendor_lib.db // elaborate and build the database

%mvrc

mvrc> read_db

4.1.2 Multi-Voltage static checks

After reading the multi-voltage database, MVRC can then perform on RTL and Netlist, without any testbench and test vectors, to statically checking multi-voltage defects, such as missing or incorrect use of protection devices, routing ctitical signals from an inactive island to an active island, etc. Traditional rule checkers cannot detect such errors as they do not understand the variability of voltage in the design process.

mvrc> report_protection –all // display comprehensive information about all the

//protection circuits that are required for the design

After MVRC checking is performed, if there is any violation, an error message will be generated. Below is an isolation missing defect that was caught by MVRC in VC08XX.

[MVRC] ERROR 9062: Protection device of type ISO_PURE is missing between

vc08xx.u_power_shut_down.path.sig_en -> vc08xx.u_power_always_on.path.en

At the end of messages, there is a summary:

Design Protection Summary:

Crossovers with correct protection : xxx

Crossovers needing protection : mm

Crossovers not needing protection : yyyy

Crossovers with illegal protection gates : 0

Incorrectly placed protection gates : 0

Crossovers with wrongly connected protection gates : 0

Redundant protection gates : z

Devices encountered in the design:

Iso pure : xxx (legal), 0 (illegal), z (redundant)

List of redundant devices:

vc08xx.u_power_always_on.u_pmu_iso.path_to_the_device.u_iso_and

One can also check the info/error/warning messages in a report file which is generate by MVRC.

4.2 Dynamic checking using MVSIM

Dynamic checking, as well as static checking, relies on MVCMP and MVDBGEN to generate a Multi-Voltage database, which is required in the power aware simulation. The difference is that power aware simulation requires a testbench and test vectors besides the power intent file and design files. In contrast to static checking, in the power intent file for dynamic checking, there is another top power island which is the testbench power island and contains all the other islands, which represent the design power domains. When the elaborated database is ready to use, the design is loaded to an industry standard functional simulator such as VCS, together with MVSIM through VPI.

Along with building the database, MVDBGEN generates a makefile (Makefile.ev) in the current working directory. One can use this file to simulate the design with any industry standard simulators such as VCS/VCSMX.

4.2.1 Run power aware simulation

To run a power aware simulation with VCS, use the “Makefile.ev” which includes another tool template makefile. Here it is VCS.

%make -f Makefile.ev all TOOL=vcs

This command internally executes the following VCS command:

vcsi +vpi -P mvsim.tab -R <compilation_options> <source_files> -load libmvsim-

vcs.so:mvsimInit -l transcript

4.2.2 Debug the design

One can use the log file, mvsim.log, which is generated by MVSIM, and simulator’s debug capability (waveforms, etc.) to debug the low-power design. In the below MVSIM log file, MVSIM indicates there are some unusual events happened at simulation time 130424330 ps. Designers and verification engineers can then go to the waveform to further check is there anything wrong.

ArchPro MVSIM

Version 2.2.5 for Linux 2.4.21-40.ELhugemem — 04 Jun, 2008

Copyright (c) 2004-2008 by Synopsys, Inc.

ALL RIGHTS RESERVED

[MVSIM] INFO 5003: MVSIM initialised in ACCURATE mode.

…

[MVSIM] INFO 5002: Real variable for Rail ‘VDD_CORE’ is ‘tb_vc08xx.MV_VDD_CORE’.

[MVSIM] INFO 5024: Signal for Indicator ‘pso_indicator’ is tb_vc08xx.u_vc08xx.path.en_isolation’.

[MVSIM] INFO 5002: Real variable for Rail ‘VDD_RTC’ is ‘tb_vc08xx.MV_VDD_RTC’.

[MVSIM] WARNING 5008: Indicator not declared. Indicator for rail VDD_RTC has not been declared.

…

[MVSIM] WARNING 5211: Signal Wiggled in INACTIVE. Signal ‘tb_vc08xx.path.locked’ wiggled( possibly

due to force/release in design) when Island is in INACTIVE state at time 130424330 ps.

[MVSIM] INFO 5104: Island state changed. Island Ivddpso state changed from SHUTDOWN to ACTIVE at time = 130424330 ps.

[MVSIM] WARNING 5209: Design state changed. In LegalStates ls, Design transitioned from XYZ_OFF

state to illegal state at time 130424330 ps,

4.3 Results

VIMICRO performed static checks on VC08XX Netlist with MVRC, which meets two core abilities identified by design and verification teams. With MVRC, VIMICRO caught several low power defects which include: isolation cell missing, redundant isolations, critical signals (which were pin pointed by MVRC) are connected from OFF domain to ON domain. And the total run time, which is about 15 minutes (including the Netlist compilation, DB generation and results generation), is very satisfying, if not attractive.

VIMICRO also performed power aware simulation using MVSIM+VCS. The dynamic checking also showed its value for below reasons.

• It can simulate the power-up and power-down ramp on the voltage rails.

• It helps to monitor the verification progress, especially when it comes to power states.

• It does not require changes on the existing simulation based verification flow. Users only need to do a little preparation work such as Multi-Voltage database building and the total overhead is reasonable.

5. Summary

In this paper we explained the need of aggressive low power design techniques and the new verification challenges that come along. Then we discussed static multi-voltage rule checking as well as power aware simulation.

VIMICRO chose MVSIM and MVRC from Synopsys to verify a low power multimedia SoC, VC08XX. Both tools showed significant value as they are able to discover low power defects, and the overheads are light. VIMICRO has decided to add MVSIM and MVRC to the verification flow.

6. References

[1] Low Power Methodology Manual, For System- on-Chip Design, Michael Keating, David Flynn, etc., Springer

[2] Synopsys Low Power Verification Tools Suite User Guide @ http://solvnet.synopsys.com

[3] ViMircor

[4] Verification Methodology Manual for Low Power, Srikanth Jadcherla, Janick Bergeron, Yoshio Inoue, David Flynn, Synopsys