Abstract
Complex power management strategies like dynamic-voltage scaling (DVS), power-gating, low-vdd standby, state-retention power-gating (SRPG[1]), dynamic voltage frequency scaling (DVFS[2]) and adaptive voltage scaling (AVS[3]) are being adopted extensively for 65nm and below. Efficiently capturing the power strategy at RTL and applying through GDSII is one aspect, while verifying it is a bigger concern. This paper delineates capturing power specification of Atheros WLAN chip at RTL in UPF and verifying DVS, low vdd standby, shutoff, missing/redundant isolation-gate and control signal violations using Synopsys low power tools MVSIMTM and MVRCTM
1. Introduction
With increasing energy constrained electronic devices in market like PDA, cell-phones, notebooks, routers, switches, modems, base-stations and ever increasing demand for features like video-conferencing, music storage, playing games, high speed network access has led to packaging more functionality on a single-chip called system-on-chip with decreased process-technologies leading to higher power-consumption. Low power techniques applied were:-
(1) Dynamic voltage scaling (DVS[4])
Figure 1: Dynamic voltage scaling
Dynamic voltage scaling is an extension to multi-vdd where in different blocks toggle between two or more voltage level ranges. For example, in figure 1, CPU can operate at any level between 1.3 volts to 1.5 volts
(2) Power-gating[5]
Figure 2: Power gating
Power-gating, shown in figure 2, is a strategy where sleep transistor is used to cut off a circuit-block when not in use. High Vth cells are used as sleep transistors to reduce leakage but they switch slower and hence give low performance
(3) Low Vdd standby[6]
In low vdd standby, voltage rail VDD of power-domain is lowered to a value that is only sufficient for retaining memory elements but not for functional operation. During this period clock is gated to power-domain.
2. Power Intent: Unified Power Format [7]
The existing design languages like verilog, vhdl do not have a mechanism for describing power connections at register transfer level. The UPF defines a language format which provides simulation semantics for verification and implementation EDA tools.
With UPF support in tools and methodology, chip engineers benefit from the following:-
(1) Partitioning the chip into multiple power-domains by mapping power-supplies at RTL
(2) Functional modeling of: Power-gating, DVS,standby, DVFS, AVS, retention (save/restore), isolation, level- shifters, voltage regulator models.
(3) Dynamic power-aware verification of strategies: ON/ OFF, low-vdd standby, DVS
(4) Static power-aware verification of: Control signals, power-rail connectivity, architectural checks[8], protection-gates
3. Atheros WLAN chip specification
Atheros WLAN chip has the following power-specification with power domain architecture shown in figure-3:
(1) Number of power domains = 4
(2) Number of voltage rails = 4
(3) Number of power control signals = 7
(4) Number of isolation control signals = 4
(5) Strategies: on, off, low vdd standby
(6) Power-states: Power-off, Host-off, Wake-up, On, Deep-sleep
HOSTIF SOC WLAN RF
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Figure 3: Power domain architecture
A change in logical signal or voltage rail transitions the chip into different states as shown in figure 4
Figure 4: Power state transition
4. Specification captured in UPF
UPF standard allowed capturing power domain specification easily at RTL which is valid through implementation. A typical specification includes power domains, power supplies, power states, isolation cells, level shifter cells. WLAN chip specification was captured easily in UPF as shown in figures 5, 6 and 7
Power domain is defined as list of hierarchical elements (instances) in the design which are powered by a particular voltage-rail. For example, in figure 5 the instance host_wrapper/rtc belongs to power-domain: HOST_IF_domain powered by voltage-rail: SVDD3 and ground: VSS
Figure 5: Power domains
Power supply network consisting of voltage rails, ground rail, voltage ports, voltage rail connectivity are defined as shown in figure 6, using UPF commands.
Figure 6: Power supply network
Each power domain has its own mode of operation. It can be on, off or in standby. And modes of power domains at a given time instant define a power state. figure 7 shows power modes namely OFF1, OFF2, OFF3, OFF4, OFF5, STDBY1, STDBY2 and power states namely S1, S2, S3, S4, S5, S6, S7, S8 captured in UPF. The transition from a power state to another forms a power state transition which is monitored by MVSIM
Figure 7: Power modes and power states
From figure 5 and figure 7, power domain WLAN (powered by rail SVDD1) and SOC (powered by rail SVDD2) can go into OFF, standby modes. Similarly, power domain HOST_IF can only go OFF.
As power domains go off their outputs float to high-Z. Active domains having signals from this off domain need to be protected from high-Z to avoid data corruption. UPF command set_isolation command was used to specify isolation rule for off domains as shown in figure 8.
Figure 7: Isolation rule
5. Verification Challenges
Following were the challenges in power domain verification:
(1) To model voltage regulator model at RTL and verify rail change
(2) To verify power up, power down sequencing of power-domains signals
(3) To verify power-modes transitions
(4) To define and verify isolation policy
(5) To find Isolation and level shifters needed
(6) To check if Isolation and level shifters are existing in the design
(7) To check isolation enable polarity correctness
(8) To find island order[9] violations
6. Results
Both static and dynamic checks were performed for complete power aware verification. Power up and down sequencing, on, off, standby modes, proper isolation were simulated using multi voltage simulator (MVSIM). Existing of redundant isolation cells, missing isolations, level shifters, isolation polarity were verified statically using multi voltage rule checker (MVRC)
Figure 9 shows MVSIM simulation result of verification challenges (1), (2), (3) and (4) in section 5 namely: power up, down sequencing, standby, deep sleep on, off and isolation rule.
Figure 9: MVSIM waveform
Note above that before soc_pwd_or_vs_1st toggles from 0 (on state) to 1 (sleep state); the outputs of SOC domain are isolated to 000 using isolation enable soc_iso_en_|. The above is correct isolation sequencing. MVSIM monitors power modes and states transitions of power domains due to changes on voltage rails and control signals. It has built-in multi voltage messages which were useful for debugging, shown in figure 10
Figure 10: MVSIM messages
MVRC was used to check items (5), (6), (7) and (8) in section-5. There were no level shifters required and isolation cells were found missing and redundant. Isolation signals polarity was found to be correct. MVRC log messages are shown in Figure-XI.
Figure 10: MVRC checks
7. Future
MVSIM and MVRC helped verify power vectors and statics checks at register transfer level with minimal set up. Same power intent file shall be used for the following physical checks: rail mismatch, wrong rail connected to isolation and level shifter cells, power-ground pins connectivity, misplacement of always on buffers, power switch connectivity, correctness of voltage port, logic port connectivity and retention rail connections.
8. References
[1] Findlay Shearer, Low Power Design Techniques, Design Methodology and Tools, Power management design line, March,21,2008
[2] T.Chen, J.Qian, J. Huang, Z.Zheng (PRC), A Power-Aware System Combining Static Compiling and DVFS, Power and Energy Systems 2007
[3] David Tamura, Barry Pangrle, Rajiv Maheshwary, EEtimes July,2007
[4] Kriszti Flautner, David Flynn, David Roberts, Dipesh I. Patel, IEM926: an energy efficient SoC with dynamic voltage scaling, Design Automation and Test in Europe Conference and Exhibition, 2004, Volume 3, Issue, 16-20 Feb. 2004 Page(s): 324 – 327 Vol.3
[5] Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay, Integrated Power-Gating and State Assignment for Low Power FSM Synthesis, isvlsi, 2008 IEEE Computer Society Annual Symposium on VLSI, pp.269-274
[6] Hobbs, J.S, Williams T.W, Reaching the limits of low power design, Volume, Issue, 21-24 March 2008, Design Automation Conference, ASPDAC 200, Page(s) 732-735
[7] Unified Power Format Standard v1.0, www. unifiedpowerformat.com/images/UPF.v1.0_Standard.pdf
[8] Multi Voltage Rule Checker (MVRC), User Guide, Synopsys low power tools suite, 2007
[9] Srikanth Jadcherla, Synopsys, Multi voltage semantics guide 2005
