Abstract

The paper introduces the post-layout simulation of a large mixed-signal design with XA-VCS co-sim solution. It describes the advantage, methodology and detail implementation based on a real design of using XA-VCS.

1. Introduction

1.1 Verification requirement of complex mixed signal design

High speed, high performance designs drive the increasing integration of analog functionality onto Mixed-Signal designs. It gives a new task to designer. That is how to do the full chip simulation for the mixed signal design to finish the completed function. That require the simulator can co-work with analog and digital design. Verifying complex analog parts including post-layout parasitics demands fast speed, high performance, SPICE accurate simulation capabilities.

1.2 XA-VCS introduce

XA simulation technology is Synopsys next-generation transistor-level simulation engine that delivers SPICE accuracy while maintaining FastSPICE performance and capacity with time to results (TTR) never seen before. Numerous revolutionary patentpending technologies, including dynamic partitioning and auto-detection enable SPICE-like accuracy while delivering over 50x performance improvement over SPICE without any tuning. XA simulation technology is a full-featured standalone transistor-level simulation engine designed to augment NanoSim and HSIM as an add-on option addressing the need of NanoSim and HSIM users for SPICE accuracy without any tuning.

VCS is the industry’s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. VCS solution’s advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, VCS Verification Library provides verification IP for today’s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. VCS solution’s powerful debug and visualization environment minimizes the turnaround time to find and fix design bugs

1.3 Design Introduce

The architecture of our design Ethernet PHY 10/100 is shown Fig.1, the digital top block is described with Verilog, come from digital team. The analog parts include two 5-bit DACs , Input Buffer , two 9-bit ADCs, Reference Circuit , 125Mhz PLL , DLL.

Fig 1: The architecture of design

The main function of this design is that the digital top control the each analog parts setting. The DACs generate different outputs depend on the codes come from the digital block. The block Input Buffer enhancement the drivability of DAC’s outputs and send the signals to ADC. The PLL and DLL generated the clock signal to digital block and ADC. Reference Circuit provides the reference voltage and bias current to ADC block and DAC block.

2. Verification challenge

Due to the large scale of our design, the parasitical parameters are an important factor that can make the analog block performance drop. So we need to do the full chip post-layout simulation. It further increases the scale of our design. It’s difficult to simulate this huge design post layout. It demands the simulator must be fast enough while maitaining analog high accuracy.

3. XA-VCS co-simulation environment

3.1 XA-VCS flow overview

XA-VCS co-simulation is a high performance mixed-signal verification solution. It enables you to simulate transistor-level blocks written in SPICE descriptions netlist file with digital blocks written in Verilog description file. It can support post-layout back-annotation simulation. Fig 2 shows the basic co-simulation flow.

Fig 2: Basic Co-simulation flow

3.2 Prepare all netlist and testbench

For use post-layout back-annotation simulation, we need:

file.sp: Ideal analog HSPICE netlist

file.spf: HSPICE netlist which include parasitical parameter

Star-RCXT can extract all above two files.

For digital verilog testbench

file.v

3.3 Setup file and script

xavcs.ctrl: XA-VCS mixed-signal simulation control file.

To run XA-VCS mixed-signal simulation, a mixed-signal simulation setup file must first be created. This file is passed to VCS during compile time, and contains the call to XA and optional mixed-signal commands.

xacmd: XA optional command script file for analog blocks.

XA-specific commands can be inserted into the netlist file or provided in a separate command script file. Use the -c switch to specify the name of a command script file.

run_xa: XA-VCS co-simulation run script.

3.4 Complie the design

The run script include the follow syntax:

“vcs -o xavcs -Mdir=csrcxa file.v -ad=xavcs.ctrl -nohsopt -l vcs.log -full64”

It invokes the vcs command.

The option “-ad= xavcs.ctrl” specify the mixed-signal simulation control file.

The option “-full64” specifies the 64bit version.

choose xa -hspice file.sp -c xacmd -o output/xa;

Example 1: xavcs.ctrl

The choose command identifies “XA” as the analog engine for co-simulation.

“-hspice file.sp” specify the hspice format ideal layout netlist.

“-c” specify the XA command script file “xacmd”.

Example 2: xacmd

“load_ba_file –file” specify the parasitic netlist file which back-annotated to the ideal netlist. “probe waveform_voltage” specifies the hierarchy level down to which the voltage is probed. “set_sim_level” controls the speed and model complexity trade-off. It can be applied for entire netlist or to specified subcircuit or instances. The argument can be set 3 to 7. The default level is 3. We set to level 6, it can supply the SPICE-like accuracy and half time consumption.

3.5 Run simulation

Fig 3 gives the visual overview of XA_VCS co-simulation flow.

Example 3: Overview of XA_VCS co-simulation flow

3.6 Analyze the results

The simulation results can be viewed by Synopsys powerful Waveview Analyzer. The 5-bit DACs output shows in Fig 4

Fig 4: DAC output

The 9-bit ADCs output shows in Fig 5

Fig 5: ADC output

In our design we expect that these 9-bit digital signals can replay the DAC output. We use D2A function provided by Waveview Analyzer to convert these digital signals to analog waveform. The result shows in Fig 6

Fig 6: Results

XA-VCS co-simulation is completed successfully. The function of our design is verified well. This simulation takes about 19 hours. It can save at least 30% time with satisfied accuracy than other co-sim solutions we used before.

4. Summary

This article describes XA-VCS co-simulation flow based on a real design. It is very helpful for mix-signal designer to reduce design time and verification iterations. According to the simulation results, we achieved a good run time performance with a satisfied accuracy.

The article just described some advantage for mixed signal simulation with XA-VCS solution, in fact, when you use it for your mixed signal simulation, you can find out more and more good feature. For example, for reducing the simulation time, you can set the spice simulation precision separately for the different analog blocks according to their different precision requirement.

I think in the future, the co-simulation with XA-VCS will be speeded up with suitable precision and speed.