Mixed-signal Full Chip Verifi cation with XA-VCS
Sun ZhaoyangCyrusSun@viatech.com.cn
Abstract
Modern deep-submicron microelectronic technologies results in a crucial issue for the whole chip verification. Our designers want to find a verification solution with well situated accuracy and acceptable speed. We tried to verify mixed-signal test cases to verify the whole chip function with XA-VCS. During pre-layout and post-layout simulation of the testcases , XA-VCS shows multiple times speed acceleration than our previous solution, which makes sure to meet our limited verification schedule. This paper introduces the XA-VCS environment and simulation result on a 40nm testcase. To satisfy mixed-signal full chip verification, we think there are some desired features to be improved. It has been described in this paper also.
1. Introduction
This paper is intended to introduce a FastSPICE simulation engine, the XA from Synopsys, and it’s co-sim solution with VCS. Hsim simulator as a mixed-signal whole chip verification solution has been adopted extensively. Circuit designer found it suitable for large and moderate scale chip verification. But as the circuit’s complexity and the signal speed increase, a new simulation engine which can offer higher speed and acceptable accuracy becomes an emergency. Recently, VIA BJ evaluated XA for pre & Post layout simulation for varies of circuits. We can get good results for our designs with XA. Also we evaluate Co-Simulation flow using XA and VCS. For custom blocks, it is necessary to verify the correlation between its behavior model and circuit design. Co-Simulation flow can be used to do this. We focus on custom blocks function check before layout and timing check after placing and routing.
2. XA-VCS environment
The XA technology is the next-generation transistor-level transient simulator that delivers out-of-box SPICE accuracy while maintaining FastSPICE performance and capacity. XA is designed to reach the need for high accuracy simulation with little commands option tuning. XA provide accelerated simulation of analog and mixed-signal designs even with full layout parasitic. It’s predictable and repeatable SPICE-accurate results improve sign-off confidence. The common HSPICE models and netlist format ensure the ease of adoption. XA provides intuitive simulation control with an accuracy setting (set_sim_level) used globally or locally. The XA can also perform co-sim with VCS with the same DKI way of Hsim & NanoSim to provide outstanding mixed-signal & mixed-language simulation capability as shown below in this paper.
2.1 XA-VCS simulation confi guration
The XA-VCS simulation environment is easy to setup. Below figure 2.1 shows the basic introduction of XA-VCS co-sim interface file.
Figure 2.1 XA-VCS co-sim interface file
Four output files below the directory of xaVcs.msv can help designer to debug the errors of analog, Digital interface nodes.
Figure 2.2 interface_element.rpt
Figure 2.3 hierarchy.rpt
Figure 2.4 name_map.rpt
3. XA-VCS testcase checkpoints
For this test case, XA-VCS Verilog-SPICE flow is used. The analog part of the design is modeled in SPICE format and digital parts are modeled in verilog format. And verilog is on the top of SPICE in the hierarchy. We focus on below points to check.
1. Interface A/D and D/A signal conversion
2. Converting Signal Strength and Resistance Map File
3. Timing accuracy check
3.1 XA-VCS Interface A/D and D/A signal conversion
The direction of the digital and analog interface is determined from verilog port direction. If a SPICE child under a verilog parent configuration without verilog view, all interface ports are recognized as inout ports. You can use a2d and d2a commands to define the uni-direction ports. At the same time, you can define its high/low voltage, threshold or rise/fall time. For real inout interface, it should be defined both as a2d and d2a signal.
3.2 Converting Signal strength and Resistance Map file
There are eight different levels drive strengths. They are listed below. Level 7 is the strongest and level 0 is the weakest. The default drive strength for interface ports is level 6.
When doing A2D/D2A conversion, the resistance map file is used. The default rmap file is listed below.
resistance_map 90000.2-1e32 0 ;
resistance_map 70000.2-90000.2 1 ;
resistance_map 50000.2-70000.2 2 ;
resistance_map 7000.2-50000.2 3 ;
resistance_map 6000.2-7000.2 4 ;
resistance_map 1000.2-6000.2 5 ;
resistance_map 1.2-1000.2 6 ;
resistance_map 0-1.2 7 ;
The eight levels driver strengths are corresponding to the resistance map eight levels. By default, resistance map is bidirectional which means A2D and D2A conversion use the same rmap file to define the analog or digital driver strength. You can also define analog to digital or digital to analog unidirectional resistance map to meet your design requirement.
3.2 .1 A2D conversion
Verilog strength is determined from the analog output resistance through resistance map file. For example, if analog output resistance 60ohm, it falls into the resistance level 6 range. So verilog driver strength level 6 is get at the digital side. You can modify the ramp file to get your pre-defined verilog driver strength.
3.2 .2 D2A conversion
Verilog driver strength is converted to analog voltage through an average resistor connected to power or ground. The average resistance is get from the resistance level range in rmap file. For example, verilog driver strength level 6 correspond a resistance value (1.2+1000.1)/2=500.65ohm.
Figure 3.1 resistance circuit of interface
In above figure, suppose verilog driver strength is level 6 and input high/low thresholds are VHth and VLth respectively. So you must guarantee following equations to get correct input signal at the analog side.
If can not meet the requirements and R1 & R2 are design targets, the rmap file must be modified to meet above equations.
3.3 Timing accuracy check
To get accurate timing check after P&R, you must set corresponding constraint from SDC file. Here we focus on input port high/low voltage and rise/fall transition time setting when performing digital to analog conversion.
As before discuss, digital signal is converted to analog voltage through a resistor connected to power or ground. And there is also an equivalent input capacitance at the analog input port. The high/low voltage is get from above equations (1) and (2) and the rise/fall transition is get from RC constant value. They are not the values you define in D2A command.
To accurately define the values, you can define the input port as power net. Under this condition, it will ignore the resistor connected to power or ground and then can get the value defined in D2A command.
4. Open issues
Most issues have been resolved under the help from Synopsys. There still have open issues lists below.
For timing check, the same path has large timing difference compared with flatten flow. Refer to below figure.
Figure 4.1 circuit description of open issue
From above figure, dout can output d1, d2, d3 or d4 through different combination of s1 and s2. When outputing different data d1~d4, the timing variation of path rclk [I1] dout can be up to 50ps which much exceeds design target.
From evaluation results, it is appropriate to use XA/VCS Co-simulation flow to do function check. It needs no modification for both digital and analog design and saves at least 50% memory usage and 50% run time compared with our old flow. For accurate timing check, co-sim flow has little lower timing accurate than pure spice simulation. So it is not appropriate for accurate timing check using Co-simulation flow.
5. Acknowledgements
We would like to give thanks to our colleague Randy Zhou and participant engineers from Synopsys. It was their greatly help to complete this evaluation. Many thanks to them!
6. References
CustomSim XA User Guide
CustomSim XA Command Reference
Discovery AMS: Mixed Signal Simulation User Guide
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