Power network analysis with PrimeRail
Qiu JinChaoJinchao.qiu@intel.com
Intel Mobile Communications Xian
摘要
在现在的芯片设计中,已经大量使用多电压域 的设计方式, 这些方式使我们芯片的功耗降低了很多,但是这种新的设计方式也给 我们带了很多的挑战, 特别是电源网络的设计。 在现在的设计中有很多个电源线, 不同电源线上的电压降以及他们之间的整合 都需要额外的验证。所以,电源线的功耗分析、电压降分析也已经成为了一个很重要的事。我们需要使用一个好的工具来分析供 电网络上的功耗和电压降。在本篇论文中,我研究了应有PrimeRail来分析和发现供电网络上电源供电问题的方法,同时也提出了 一些需要在布局布线时注意的影响电压降的因素,考虑这些因素有助于减少设计的重复次数。
Abstract
Having completed the implementation of the multi-voltage, voltage island, power gated design, it helps us a lot to reduce the power consumption. However, the new design style also brings forward new challenges, especially to the designers of power/ ground (P/G) networks. There will be many power rails in the design, the integrity of each power network needs to be verified and the voltage drop on the power network also needs to be verified. Performing power rail analysis of the design becomes to a critical thing now. Using a comprehensive rail analysis tool, we can perform extensive analysis of the power networks in the design. In this paper, I study the detection of the power delivery problem in the whole power network and the voltage island designs by using PrimeRail, and also give some proposals to consider voltage drop during the floorplanning process to reduce design iterations.
Keywords: Power Domain, Static IR_drop, power switch cell, switch off
1. Introduction
The design for multiple supply voltages (MSV) has become a popular choice to satisfy modern low power design requirements. However, voltage island design style brings forward lots of new challenges that must be carefully handled to ensure a successful design. The challenges include:
1. Each voltage island will have dedicated (or partial dedicated) power supply network, the power network will not connect together normally, so the power supply for each network need to be guaranteed.
2. Due to the complexity of the design, there are lots of hardmacros in our design now. In order to consider the timing/power supply/floorplan of these hardmacros, the floorplan of the submodules can’t be regular shape anymore. So lots of corners and channels may not get enough power supply or even miss the power supply.
Due to these complex challenges, it’s quite easy to cause big static IR_drop or power net connection issue in our design, so we need perform the Rail voltage analysis to find out the power propagating issues and reduce the IR_drop.
2. Analysis Flow
PrimeRail can be used at different points in the design flow after floorplan is performed to verify the power supply network to find power network issues in design early stage and solve them. This capability can help us to detect potential violations before we perform detailed placement and routing and thus significantly reduce turnaround time later in the design cycle.
Here is the basic flow for running the PrimeRail after finish step, we already have the detail routing at this step, so the RC information and routing information is accurate, we can then calculate total power consumption and check for voltage drop and electro-migration violations on a circuit.
1. We can use the mission mode STA database, and define the toggle ratio for all the clocks. Then we can enable the power analysis in PTPX and generate the power information for each standard cell with commands:
set power_enable_analysis true
set_switching_activity -clock_derate 0.1 -static_probability 0.5 -clock_domains [all_clocks] -type register -hierarchy
set power_rail_output_file cell_power.rpt update_timing update_power
2. In order to generate the power setup file “synopsys_pr_ setup.e” in ICC, we need collect the Milkyway database for all the modules, and we should have CEL view, ILM view and FRAM view inside the Milkyway database. Meanwhile, the DB view and the CONN view also should be ready for all the libraries which is used to indicate the timing and power connection in the libraries cells. After collecting the entire database, we can generate the power setup file by using ICC command:
create_rail_setup -parasitic_corner max –directory power_setup_results
3. Then we can start to extract the power network in PrimeRail. Of course, as we may have several voltage areas in our floorplan, that means we will have lots of different power nets. So we need indentify the power nets here to tell the tool which power nets we want to extract. The commands for this step are:
poLoadRailSetup
setFormField “Load Rail Setup” “File Name” “power_setup_results/synopsys_pr_setup.e”
formOK “Load Rail Setup” poExtractPGParasitics
setFormField “PG Net Extraction” “PG Net Name” “$PG_NETS”
formOK “PG Net Extraction
4. After getting all the information above, one more thing need to do before starting to run the IR_drop analysis in PrimeRail is to list the power sources, we need tell the tool the location of our power sources. Now we can start to run the static IR_drop analysis in PrimeRail with commands:
poTransientPowerAnalysis
setFormField transient_power_analysis power_vector-free_report_file cell_power. rpt
formOK transient_power_analysis poRailAnalysis
setFormField “P/G Rail Analysis” “power_ net_name” “$power_net”
setFormField “P/G Rail Analysis” “pad_ name_file” “PG_source.txt”
formApply “P/G Rail Analysis”
The tool can then generate the IR_drop reports and schematics for each power net.
3. Common issues of Power Network
With a physical topology in place we can now begin to consider how to provide power to the various voltage areas in the design. Since by definition, each power domain employs a different power strategy, it is likely that we will be routing different power rails to each voltage area. Minimizing the voltage drop across each of these power rails is a key part of meeting the performance goal. Unfortunately, many of the techniques that we employ in a low power design can make the voltage drop and noise problem worse. Here are some common power supply issues which may cause big IR_drop:
1. Floating power/ground nets.
The floating power/ground nets will be indicated as gray color in PrimeRail, there is no power supply for them. So it is important to check in detail on these floating power/ground nets, as you may miss the power supply for the hardmacros or even the standard cell rails.
2. No terminals for power ports of submodules
Due to the complexity of the current SOC design, we will use bottom-up design flow normally. In order to propagate the power supply, we need create the terminal for all the power ports at submodule level, and then the toplevel can propagate the power supply through these power pins. This following schematic indicates that if we miss the power terminals for the power ports at submodule level, the power can’t propagate through these power ports directly, and cause big IR_drop here. It may be not a real issue here, as even we don’t define the ports as terminal, we should still have the correct connection already, it just because the tool can’t understand the connection if there is no terminal there.
Before creating power meshes as terminals After creating power meshes at terminals
3. Missing power connection for switch off nets.
We need make sure that all the switch off nets need to have pow standard cell rails which are rounded by red color, and there is a rails, then there will be no power supply for these standard cell power supply nets to connect these standard cell rails.
4. Missing VIAs (usage of “query power command”)
If the power supply can’t propagate through a part of the power network, then it may be caused by missing VIAs in the power network. For debugging this issue, we can use a good feature of the PrimeRail. When the power map is displayed, you can check for the power consumption values of a hot spot. To do this, click Query at the top of the Display Map dialog box and then click a spot in the cell editing window. PrimeRail writes the values to the log and the command window. The following is an example of querying power consumption values:
Map = Power
——————————–
clk: bBox = (121.200 251.600) (129.200 259.600)
power = 0.332 mW, power density = 0.00518 mW/um^2
[ Power density map - cell-based ]
The same as [ Power map ]
[ Power density map - window-based ]
- area query Map = Power
——————————–
clk!6: bBox = (121.200 251.600) (129.200 259.600)
power = 0.332 mW, power density = 0.00518 mW/um^2
clk!12: bBox = (107.600 251.600) (115.600 259.600)
power = 0.278 mW, power density = 0.00434 mW/um^2 \m40_reg[10]: bBox = (113.200 242.800) (130.000 250.800)
power = 0.0344 mW, power density = 0.000256 mW/um^2
—————————————————
Total power under selected area = 0.644 mW
5. No enough power switch cells.
The power propagation for the switch off net is from power bump at toplevel —> power meshes at toplevel —> power terminals at submodule level —-> power meshes at submodule level —> power switch cells —> switch off standard cell rails. So if the IR_drop of the whole switch off nets inside switch off domain is too high, normally, there are two possible reasons:
(1) The power bump is too far away from this submodule, the IR_drop of VSS net is already quite high before reaching this submodule.
(2) There are no enough power switch cells to supply the switch off nets. Then the IR_drop on the VSS off pin of power switch cell is already quit high, so it’s necessary to add more power switch cells inside this switch off domain.
If you can’t see one connecting layer in the report, and the gap of the IR_drop value on the above and below layer is quite big, most likely, you miss one layer here.
6. Power nets short
If it is analyzing one power supply net, but another power supply net is also highlighted, then that means these two power supply nets are short together. So we can just check the connection of one related cells to confirm whether the power supply nets are short together, and fix them if it’s necessary.
7. No enough VDD/VSS bumps/power meshes.
If everything looks good enough, but there are still big IR_ drops. Then it may due to the long distance to the power supply source. So it’s necessary to add additional power bumps on the critical area.
8. Power supply net is too far:
We need guarantee the distance between standard cells and power supply nets is not too long. The standard cell on this blow rail is too far from the power supply net at right side and will not get enough power supply. There is only one standard cell on this standard cell rail at that time, so the IR_drop is still ok on this rail. If there are several cells on this rail, the IR_ drop for this rail will become quite big. So we need remove this rail or add more power supply for this rail.
4. Recommendation
Based on the experience of checking the power supply issue by using Primerail, I summary the checklists we need take care at power network synthesis step. By taking caring these issues, we can reduce the power supply issues, and reduce the iteration of reducing static IR_drop.
For switch off domain:
1. Check the switchoff standard cell rails near the boundary to make sure each rail has power switch cell or other switchoff layer connection.
2. Make sure there is no floating switchoff standard cell rails. (Especially in channel or near the boundary)
3. Make sure there is one additional layer connection for all the switchoff nets, otherwise, the switchoff nets will be floating. And the switchoff layer connection should be complete, no broken points, no open points.
4. Make sure the distance from standard cells to power switch cells is not too far (the distance should be smaller than the half distance of the pitch of your power supply nets)
General:
1. Make sure there is no floating VSS/VDD standard cell rails.
2. Make sure each standard cell has power supply. (Especially the filler cells/std cells in channel/boundary)
3. Make sure there is no power short for the pins of hardmacros and pads.
4.Make sure you create the power meshes of each submodule as terminal inside the ILM.
5. Make sure you already create the top layer of pad pin as terminal in submodule level if you have pad inside the submodules.
5. Conclusion
The rail analysis gives us valuable data on the voltage drop seen by every standard cell in the design. Where we have an unacceptably large voltage drop, it’s easy to find out the power supply issues by using the PrimeRail even several power domains are used. By fixing the issued detected by PrimeRail, we can guarantee the power supply for each cell and reduce the static IR_drop to an acceptable value. And it’s also important to reduce the IR_drop to a reasonable scope. Reasonable voltage drop value for a design can then guarantee the accuracy of the static timing signoff.
Thanks for the efficient support from my manager Chen Xun, David and Synopsys AE Du Guangshan and Li Yue, they give me a lot of support on the principle of power supply and the usage of PrimeRail tool.
Rreference:
[1] TANG Zhanghong, YUAN Jiansheng. “Combination Approach of FEM and Circuit System in IR Drop Analysis and Its Applications”, in TSINGHUA SCIENCE AND TECHNOLOGY ISSN, 1007-0214, 18/18, pp850-857 Volume 13, Number 6, December 2008
[2] Zahi Abuhamdeh, Bob Hannagan, Alfred L. Crouch and Jeff Remmers. “A Production IR-Drop Screen on a Chip”
[3] Qiang Zhou, Jin Shi, Bin Liu, and Yici Cai. “Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs”, in IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
[4] Wang Xiao, Mao Junfa, Li Xiaochun. “A Static Voltage Drop Analysis Method of Standard Cell Chip”, in JOURNAL OF SHANGHAI JIAOTONG UNIVERSITY, Aug. 2007
[5] PrimeRail User Guide, version E-2010.12, December 2010.
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