Signal Electro-migration Analysis and Fixing Research in IC Compiler
Xiaotao Maxima@nvidia.com
Jiangbin Xiejixie@nvidia.com
Chandler Meicmei@nvidia.com
NVIDIA Semiconductor Technology Corporation
Abstract
With technology scaling down for integrated circuits, electro-migration (EM) has become a serious chronic pitfall under deep sub-micron process. It not only affects power distribution network, but also has deep impact on clock/signal interconnection. So clock/signal EM deserves more attention. In principle, EM violations are caused by high current density which is related to routing width, transition, load and so on. These factors affect with each other and determine the performance of the IC.
This paper focuses on clock/signal EM analysis and fixing methods in IC Compiler. Firstly, detailed analysis of each factor related to clock/signal EM is present. Secondly, based on IC Compiler environment, some methods are proposed to fix clock/ signal EM violations while minimizing degradation of other metrics. Then, some experiments and comparisons are performed in IC Compiler to demonstrate the effectiveness of various methods. Finally a conclusion is drawn on our recommendation to fix clock/signal EM by IC Compiler.
1. Introduction
Although the scaling of digital CMOS IC technology node continues as Moore’s law indicates, larger DC/AC current will be introduced in many high speed ASICs such as GPU and CPU. Therefore, electro-migration (EM) has become a serious chronic pitfall which not only affects power distribution network, but also has deep impact on clock/ signal interconnection.
In principle, EM violations are caused by high current density which is related to routing width and length, transition, load and so on. These factors affect with each other and determine the performance of the IC. For instance, strict transition determined by driver strength, load and their interconnection will improve setup timing, while making it difficult to satisfy EM rules.
This paper focuses on signal EM analysis and fixing methods in IC Compiler. Section 2 will indicate the mechanism of EM and give detailed analysis of each factor related to signal EM. Based on the theory analysis, four feasible methods are proposed in the perspective of physical design engineers. Adopting wide or non-default-rule (NDR) nets is the most direct and effective way, which makes the transition a little bit worse due to the increasing net parasitic capacitance. Another way is sizing down the driven cell to increase the equivalent output resistance if there is enough margin for transition. Splitting the fan-out to decrease the load capacitance will improve both EM and transition in the cost of die area and power consumption. The fourth method is to shorten the net length by moving cells, which is not impractical at the last stages of physical design. In section 3, the four possible methods are verified one by one in a test case based on IC Compiler environment. All the experiments results are listed for comparison, and then recommended methods for different cases are given. After that, the available options for fixing EM violations in ICC are demonstrated in a real design. The effectiveness and side effects are both given for reference. Section 4 draws a brief conclusion for fixing clock EM.
2. Theory analysis of signal EM
Electro-migration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. Electro-migration decreases the reliability of ICs. In the worst case it leads to the eventual loss of one or more connections and intermittent failure of the entire circuit.
Figure 1 – Failure Mechanism of electro-migration
2.1 Characterization of signal electro- migration
According to Black’s equation, the mean time to failure (MTTF) of a semiconductor circuit can be expressed as below:
In this equation, A is a constant, J is the current density, n is a model parameter, Ea is the activation energy k is Boltzman constant, T is the absolute temperature in K.
For alternating current, some of the damage induced in the positive half-cycle can be healed in following negative half cycle due to current reversal. So the Black’s equation of alternating current should be expressed as:
This is called damage healing effect. J+ is the current density in positive half cycle. J- is the current density in negative half cycle, γ is healing factor. For pure AC signal, if duty factor is 50%, and frequency is very high, the γ tending to 1, and MTTFAC tending to infinity. IC Compiler also provides a healing factor to characterize the impact of damage healing effect. It is helpful to filter some false EM violations.
This equation flexibly describes the failure rate dependence on the temperature, the current density, the specific technology and materials. For physical design, the technology, materials and temperature are difficult to control. So we commonly convert EM requirement to current density requirement.
Figure 2 – Relationship between alternating voltage and alternating current
There are 3 representatives for alternating current:
1. Peak current:
2. Average current: I_avg =
3. Root mean square current:
Where ts is the transition time of the signal voltage u(t), whose amplitude is V; C is the effective load capacitance and f is the frequency of the signal. The peak current I peak is too pessimism when used to represent EM and the average current of normal digital signal is zero. Actually, I rms is the most practical and reasonable value for evaluating signal/ clock EM. In IC Compiler, we can use command below to control which type of current to use:
set_em_options–violation_rule_types {mean|abs_ avg|rms|peak|auto}
By default, the value is “auto”, which means that all the rules with constraints defined in the libraries are applied.
2.2 The important factor related to signal EM
Figure 3 – Modeling of EM and corresponding equivalent circuit
Figure 3 shows simple model of EM and the corresponding equivalent circuit. As depicted in Fig. 3(b), Ron is the equivalent output resistance of buffer, R wire and C wire are the equivalent resistance and capacitance of the net respectively, and C L is the input capacitance of the next stage. Combining with the formula of equivalent current, we can get:
Considering the output pin of the buffer, we know the transition time ts can be expressed asSo
In fact, Cwire consists of parallel plate capacitance, ground capacitance and coupling capacitance between wires. At nano-meter level, C coupling is coarsely equal to C wire, C ground and C parallel plate are very small. Commonly we turn on SI when analyzing and fixing EM, so we only consider of coupling capacitance in later analysis.
Using width(W), length (L) and thickness (d) to represent capacitance and resitance:So
The above formula express the input of receiver, based on them, we obtain the approximate expression at output of driver, which is more critical to signal EM:
Although there are many factors related with signal EM, in the perspective of physical design engineer, only four parameters are controllable for fixing EM:
1) Width of wire (W): The equation of J rms shows that increasing width is the most efficient way to reduce current density. The transition ts at the output of driver maybe degrade, but ts at the input of receiver can get optimal when:
(2) On resistance of driver (Ron):
When having margin for slew, using smaller cells to increase R on will decrease J rms, and hence, is helpful to EM.
(3) Load capacitance (CL):
Load capacitance is positive related to both current density and transition time. So splitting fan-out can do good to EM and slew if area and power permit.
(4) Length of wire (L):
Although shorter length will definitely improve EM and slew, it is impractical at the later stages of physical design.
3. Signal electro-migration fixing in IC Compiler
3.1 EM fixing experiment in IC Compiler
Figure 4 – Layout of the EM test case in IC Compiler
In order to demonstrate the effect of each factor, Fig.5 shows a test case including only a few buffers and flip-flops in IC Compiler. Each factor (W , L , CL , and R on) is evaluated separately in respect to both current density and transition time at the same node.
Before reporting signal EM, we need call “set_em_option” to define options for EM violation reporting and fixing:
set_em_options
-healing_factor 1.0
-violation_rule_types rms
-analysis_effort medium
-min
-max
Then we use “report_signal_em” to report the EM effect (current density):
report_signal_em
-verbose
-significant_digits 2
$n
Figure 5 – Signal EM report in IC Compiler
We can see that the EM report is comprehensive and succinct. Apart from the current, it also reports the transition of driver pin which is closely related with EM. What’s more, IC Compiler calculates full transition (0-100%) instead of point to point transition (30%-70% or 10%-90%), so the transitions in this report are larger than STA transitions. Under this way, the result of signal EM report is more close to the real situation. For current value, if the segment is long, ICC will report a value by each certain distance (about 50u) rather than calculating driver pin point value only or calculating an average value, which is more accurate.
Besides, we use “report_timing” to report transition and net delay:
report_timing
-nets
-transition_time
-capacitance
-input_pins
-from DATAIN
-significant_digits 7
We select all data and filled them in table below:
Table1 – Effect of each factor when reference length is 10u
Table2 – Effect of each factor when reference length is 40u
In sum, increasing width of wire (W) is one of the most effective and convenient method to fix EM. In IC Compiler, “fix_signal_ em” can be used to widen the violated signal wires. Sizing down driver is another good method. But we should be cautious to keep transition time meet the target when using this method. IC Compiler also supports this method, but not as a default setting. Decreasing load capacitance can also improve EM, but it needs to touch a bit more in layout (inserting new cells and wires). Decreasing length of wire (L) is helpful to both EM and transition time. What’s more, because of the existence of mechanical stress, EM damage will be counteracted when L is less than “Blech length”. But it affects placement and timing greatly so that it is difficult to perform.
3.2 General methods of signal electro-migration fixing in ICC
3.2.1 Widening wire
In IC Complier, we generally use “fix_signal_em” to fix EM violation:
fix_signal_em
[-max_number_iterations count]
[-only_segment_size]
[-only_net_ndr]
[-only_cell_based]
[list_of_nets]
-only_* options are exclusive with each other. By default, only_segment_size is on, it only size up violated wire segment or via (shown as picture 7), the routing has little topology changed.
Figure 6 – Segment-based signal EM fixing in IC Complier
If option only_net_ndr used, it uses only rerouting with non-default routing rules to repair EM violations (shown as Fig.8). Nets with EM violations are rerouted with non-default routing (NDR) rules applied. The applied NDRs are removed after fixing is performed.
Figure 7 – NDR-based signal EM fixing in IC Complier
Both of these two methods fix EM violation by widening width of wires.
We selected a block in our design, in which there are ~700K instances. We performed these two methods respectively and collected the results of them as below:
Table 3- The results of two EM fixing methods
We can see that when using option only_net_ndr, DRC number increase. In the meantime, the performance of EM fixing is a bit worse than using option only_segment_size, it is caused by the net capacitance increasing.
3.2.2 Sizing down driver cell
If option only_cell_based used, it performs only cell resizing to repair EM violations. The cells that drive nets with EM violations are resized smaller to eliminate or reduce the violations. In fact, this method fixes EM violation by increasing the on resistance (Ron) of driver cells.
In our design, almost all of the EM violation appeared on clock nets. To prevent clock slew and skew deterioration, we didn’t try this method.
4. Conclusions
IC Compiler shows outstanding performance on signal EM analysis and fixing. It presents comprehensive, accurate, and actual EM information in a succinct format, and takes damage healing effect and full transition into consideration to filter the false EM violations. What’s more, multiple options are available for EM fix in special cases:
(1) Widening violated segments: this is the most effective, convenient and recommended method;
(2) Widening the whole violated wire: this method is a little bit worse than method (1), but still is an effective method;
(3) Driver Downsizing: need to be cautious of transition time.
5. Acknowledgements
We are heartily thankful to Chandler Mei and Qingyuan Zheng, who give us many guidance, support, and encouragement. What’s more, I offer my regards and blessings to all of those who give us help and suggestions.
6. References
1. Black, J.R. (1969). “Electro-migration – A Brief Survey and Some Recent Results”. IEEE Transaction on Electron Devices (IEEE) ED-16 (4): 338.
2. Jiang Tao, Jone F. Chen, Nathan W. Cheung, and Chenming H. (1996).”Modeling and Characterization of Electro-migration Failures Under Bidirectional Current Stress” . IEEE transactions on electron devices, vol. 43, NO. 5.
3. Petrescu, V. and Mouthaan, A.J. and Schoenmaker, W. and Salm, C. (1998) Mechanical stress evolution and the blech length : 2D simulation of early electromigration effects. Microelectronics Reliability, 38 (6-8). pp. 1047-1050. ISSN 0026-2714
4. Jan M. Rabaey, Anantha Chandrakasan. “Digital Integrated Circuits” chapter 4.3-4.4, P100-P115, ISBN 7-121-00383-X 5. Jens Lienig “Invited Talk: Introduction to Electromigration-Aware Physical Design”
7. Appendix
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