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Speedy Simulation for Mixed-Signal Circuits With XA-VCS


Ming ShiKnight.shi@amlogic.com

Amlogic (shanghai) Inc

Abstract

As the process goes to deep submicron even nanometer, the design of integrated circuit is more complicated. To reduce the area, more and more function blocks are implemented by mixed-signal circuits. These bring challenges for designers in design and verification process. This paper gives a brief introduction for the mix-signal circuit simulation with XA-VCS. A PLL which include some digital modules and analog modules is simulated with the proposed simulation flow. After carefully comparing the simulated results, we can get the accurate results. At the same time, the simulation time is only one fifth compared to traditional simulation flows.

1. Introduction

As the process goes to the nanometer, tens of millions gates can be integrated into one chip and the functions of the chip are more complicated. At the same time, more and more mixed-signal circuits were designed to take account into the digital circuit benefit. For the designers, we have to design and verification more complicated mixed-signal circuits accurately and efficiently. But it always needs us to spend plenty of time on it. Unfortunately, the market does not wait for us. In this paper, we will introduce using XA-VCS verification flow to verification a PLL which include the analog blocks and digital blocks. It can accelerate the simulation process.

2. A mixed signal circuit description

A phase locked loop (PLL) is used as a sample to describe how to use the XA&VCS verification flow. The block diagram is shown in figure 1. The PLL consist of PFD, charge pump, loop filter and VCO. These blocks are analog circuits. A digital block was used to pre-setting the VCO to accelerate the locking process and enlarge the VCO frequency range.

Figure 1 block diagram of the PLL

3. XA-VCS co-simulation design flow

3.1 XA and VCS introduction

XA simulation technology is Synopsys next-generation transistor-level simulation engine that delivers SPICE accuracy while maintaining Fast SPICE performance and capacity with time to results (TTR) never seen before. Numerous revolutionary patent pending technologies, including dynamic partitioning and auto-detection enable SPICE-like accuracy while delivering over 50x performance improvement over SPICE without any tuning. XA simulation technology is a full-featured standalone transistor-level simulation engine designed to augment NanoSim and HSIM as an add-on option addressing the need of NanoSim and HSIM users for SPICE accuracy without any tuning.
VCS is the industry’s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. VCS solution’s advanced bug-finding technologies include full-featured Native Test bench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, VCS Verification Library provides verification IP for today’s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. VCS solution’s powerful debug and visualization environment minimizes the turnaround time to find and fix design bugs

3.2 XA-VCS flow overview

XA-VCS co-simulation is a high performance mixed-signal verification solution which adopts Synopsys proprietary DKI (Direct Kernel Interface) with up to 15% performance improvement over VPI (Verilog Procedural Interface). It enables the users to simulate transistor-level blocks written in SPICE descriptions netlist file with digital blocks written in Verilog description file. It can support post-layout back-annotation simulation. Figure 2 shows the basic co-simulation flow.

Figure 2 Basic co-simulation flows

3.3 Spice netlist and Verilog HDL file preparation

After the schematic is ready, we can extract the spice netlist by tools. Also the netlist including the parasitic parameters can be involved. For Verilog HDL file, we can use the .v file to run the simulation. If we need run the digital blocks with timing information, CDL file is also supported. In the test bench, except the ideal signal generator, the ideal function blocks described with Verilog-A is well supported also. We can just add the Verilog-A file into the configuration.

3.4 co-simulation configuration setting

XA command file: It defines the different simulation accuracy for each block and other simulation related items.

Figure 3 Sample configuration for command file

XA-VCS cosim configuration file: It chooses the analog simulator to simulate SPICE netlist and SPICE as top level block. At the same time, we can define the AD and DA interface between the analog module and digital module.

Figure 4 Sample configuration for cosim configuration

XA-VCS co-simulation run script:
vcs +ad=cosim.cfg +vcs+dumpvars PRE_SETTING.v -l vcs.log

3.5 Simulation results

After few hours, the simulation will be finished and co-simulation waveform is available. Figure 5 is the total lock behavior of the PLL. Figure 6 is the zoom in pictures of the output signals’ frequency.

Figure 5 Locking behavior of PLL

Figure 6 Zoom in output clock frequency

4. Conclusion and acknowledgement

This PLL is designed using SMIC 65nm process. The input clock source is 24MHz and output frequency is up to 2GHz.The loop simulation is always a bottleneck for our design and verification. Use traditional spice tool to simulate the whole loop will spend couple days, even more with parasitic parameters. If we use the proposed XA-VCS co-simulation solution, the simulation time will be only one fifth compared to traditional tools. From the figure 6, we also can see that the simulated accuracy is satisfied. Although the circuit of this case is not very complicated, we are impressed by the efficiency and accuracy of the proposed XA-VCS co-simulation solution. It gives us confidence to run the simulation for the larger circuits with one or more functional blocks, even the whole chip.
We would like to especially thank the great support of Sean Zhong, Lawson Yin and Jack Zeng from Synopsys.

5. Reference

1. XA User Guide, Version D-2010.03, March 2010
2. XA Command Reference, Version D-2010.03, March 2010
3. Discovery™ AMS: Mixed-Signal Simulation User Guide, Version D-2010.03, March 2010
4. http://www.prnewswire.com/news-releases/synopsys-mixed-signal-verification-solution-delivers-5x-speed-up-at-amlogic-118000819.html

6. Appendix

http://synopsys.mediaroom.com/index.php?s=43&item=910
Synopsys Mixed-signal Verification Solution Delivers 5X Speed-up at Amlogic
CustomSim and VCS Solution Enables Fast Turnaround Time for SoC Verification
Mar 15, 2011
MOUNTAIN VIEW, Calif., March 15, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Amlogic, a leading fabless supplier of video, audio and image processing chips, has selected Synopsys’ CustomSim™ solution for mixed-signal verification of its high-performance multimedia system-on-chips (SoCs). Using CustomSim and VCS®, Amlogic observed a 5X improvement in verification throughput compared with competitive solutions, helping to reduce the typical SoC verification cycle from five days to 21 hours.
“Amlogic’s new AML8726-M multimedia SoC combines our proprietary HD multimedia processing engine with ARM® Cortex™-A9 MPCore CPU and Mali™-400MP GPU cores, setting a new standard for high-performance SoCs,” said Mike Yip, vice president of Engineering at Amlogic. “Synopsys enabled us to meet aggressive tapeout schedules by reducing our chip-level mixed-signal verification time by more than 5X with CustomSim and VCS while ensuring high-quality verification.”
CustomSim, an integral part of Synopsys’ Discovery™ Verification Platform, unifies the best-in-class NanoSim®, HSIM® and XA FastSPICE technologies with added multi-threading capabilities for high-capacity, high-performance circuit simulation. For full-chip mixed-signal verification, CustomSim is tightly coupled to the VCS functional verification solution through Direct Kernel Integration and is integrated into a unified analog/mixed-signal (AMS) verification environment, simplifying usability through a common set of inputs, outputs and device models.
“Designers have consistently ranked mixed-signal SoC verification throughput as one of their top areas to improve,” said Bijan Kiani, vice president of product marketing at Synopsys. “The combination of CustomSim and VCS delivers the performance and capacity needed to run full-chip mixed-signal verification of multi-million-gate designs, allowing our customers to shorten tapeout schedules and increase confidence in verification quality.”
About Amlogic
Amlogic is a leading fabless system-on-chip (SoC) company that provides open platform solutions for HD multimedia, 3D gaming and internet connected consumer applications including tablets, digital TV, set-top box, IP-STB, digital photo frame and MID. Amlogic has combined its proprietary HD multimedia processing engine and systems IP with industry-leading CPU and graphics processor technology to produce semiconductor (IC) solutions for leading OEM and ODM brand customers in the world. Amlogic provides a total integrated solution to its customers so that they can bring compelling products to consumers in fast time to market. By providing SoC solutions with high-level of system integration, Amlogic enables its customers to quickly produce connected CE products that can reach a good balance between advance feature performance, power consumption and cost. The company is headquartered in Santa Clara, California, with offices in Shanghai, Shenzhen, Beijing and Hong Kong. Visit Amlogic online at http://www.amlogic.com/.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
Synopsys, CustomSim, Discovery, HSIM, NanoSim and VCS are registered trademarks or trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners