培训日程
Workshop Schedule 2010
| Date | Course Name | Location |
| Jan 13~15 | PrimeTime 1 | Beijing |
| Jan 20~22 | DFT Compiler 1 | Shanghai |
| Jan 29 | IC Compiler 2: CTS | Shanghai |
| Feb 2~3 | HSIM | Beijing |
| Feb 3~5 | Design Compiler 1 | Shanghai |
| Feb 5 | SystemVerilog Assertion | Shenzhen |
| Mar 2~3 | HSIM | Shanghai |
| Mar 9 | PrimeTime 2 – Debugging | Shanghai |
| Mar 12 | IC Compiler 2 – HDP | Shanghai |
| Mar 17~19 | IC Compiler 1 | Shenzhen |
| Mar 24~26 | SystemVerilog Testbench | Shanghai |
| Mar 29~31 | IC Compiler 1 | Beijing |
| Apr 1~2 | CustomSIM | Shenzhen |
| Apr 9 | TetraMAX 2 | Shanghai |
| Apr 15~16 | Power Compiler | Shanghai |
| Apr 21~23 | PrimeRail | Beijing |
| Apr 29 | Design Compiler – Topographical | Shenzhen |
** Synopsys reserves the right to cancel or re-schedule the workshops **
Please go to http://inter.viewcentral.com/reg/Synopsys/search and select the course listed in the table for course details.
Daily Class Time: 9.00am – 5.00pm
Registration
City: Beijing
Registration can be made by contacting Dai Jingwen at email: jwdai@synopsys.com or
Tel: 86-10-5986 0651
City: Shanghai
Registration can be made by contacting Akira Yuan at email: hbyuan@synopsys.com or
Tel: 86-21-2307 2082
City: Shenzhen/Hong Kong
Registration can be made by contacting Jojo Wang at email: jojowang@synopsys.com or
Tel: 86-755-8251 9800
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